adderfms.v

Verilog作业 ：自己写的源码输入

//Author : SpAcW (I'm a chinese student ,hah~)
// If you are a member of IC design ,I would like to be your buddy!
// Email : [e-mail]

module adderfms(clk,rst,start,a,b,sum,overflow,finish);
    input clk,rst,start;
    input [4:0] a,b;
    output [4:0] sum;
    wire [3:0] asum;
    output overflow;
    output finish;
    wire flag;
    reg cin;
    reg finish;
    
    reg [5:0] state;

    reg [3:0] atmp,btmp;
    
    parameter [5:0] IDLE=6'b000001,
               Ap =6'b000010,		// judge the flag of input A
               An =6'b000100,		// A's base-minus-one's complement
               Bp =6'b001000,		// judge the flag of input B
               Bn =6'b010000,		// B's base-minus-one's complement
              END =6'b100000;		// compute the final result
    
    
    always @ (posedge clk or  negedge rst)
       if(~rst)
          begin
             state<=IDLE;
         end
       else
          begin
      case(state)
           IDLE:begin
                  if(start==1'b1)
                     begin
                         cin<=1'b0;
                        atmp<=5'b0;
                        finish<=0;
                        btmp[3:0]<=a[3:0];
                        state<=Ap;
                        
                    end
                 end
           Ap:begin
                   if(a[4]==1)
                     state<=An;
                   else
                   begin
                      state<=Bp;
                  end
                     
               end
           An:begin
                   cin<=1'b1;
                  btmp<=~a[3:0];
                  state<=Bp;
              end
           Bp:begin
                     if( b[4]==1)
                     state<=Bn;
                 
                   else
                   begin
                   cin<=1'b0;
                   atmp<=asum;
                   btmp<=b[3:0];
                      state<=END;
                  end
              end
           Bn:begin
                   cin<=1'b1;
                  btmp<=~b[3:0];
                  if(cin==1)
                     atmp<=asum;
                  
                  state<=END;
               end
           END:begin  //???????????
                      finish<=1;
                      state<=IDLE;
                end
        default:begin
            state<=IDLE;
        end
   endcase
         end
         

      
      
      assign sum={flag,asum};
    
    adder ad(.a({a[4],atmp}),.b({b[4],btmp}),.sum(asum),.cin(cin),.flag(flag),.overflow(overflow));
    
endmodule