adder.v

Verilog作业 ：自己写的源码输入

//Author : SpAcW (I'm a chinese student ,hah~)
// If you are a member of IC design ,I would like to be your buddy!
// Email : [e-mail]

module adder(a,b,cin,sum,flag,overflow);
    input [4:0] a,b;
    input cin;
    output [3:0] sum;
    output flag;
    wire co;
    wire f1;
    output overflow;
    
    wire [2:0]c;
    
        assign c[0]=((a[0]|b[0])&cin)|(a[0]&b[0]);
        assign c[1]=((a[1]|b[1])&c[0])|(a[1]&b[1]);   
        assign c[2]=((a[2]|b[2]))&c[1]|(a[2]&b[2]);
        assign co=((a[3]|b[3])&c[2])|(a[3]&b[3]);
        assign sum[0]=a[0]^b[0]^cin;
        assign sum[1]=a[1]^b[1]^c[0];
        assign sum[2]=a[2]^b[2]^c[1];
        assign sum[3]=a[3]^b[3]^c[2];
        assign overflow=((~a[4])&(~b[4])&(co))|(a[4]&b[4]&(~co));
        
        assign f1=((a[4]|b[4])&co)|(a[4]&b[4]);
        assign flag=a[4]^b[4]^f1;
        
endmodule