add_top.v

Verilog作业 ：自己写的源码输入

//Author : SpAcW (I'm a chinese student ,hah~)
// If you are a member of IC design ,I would like to be your buddy!
// Email : [e-mail]

`timescale 1ns/1ns

module add_top;
    reg [4:0] a,b;
    reg rst,start,clk;
    wire [4:0] sum;
    
    wire overflow;
    wire finish;
    
    initial 
       begin
           clk=0;
           rst=1;
           start=0;
           a=5'b10001;
           b=5'b00001;
           #5 rst=0;
           #10 rst=1;start=1;
           #20 start=0;
       end
       
       always #10 clk=~clk;
       
       always @(posedge finish)
          begin
              #15 a=$random%32;
              	  b=$random%32;
		  start=1;
	     #10  start=0;
         end
    
    adderfms af(clk,rst,start,a,b,sum,overflow,finish);
    
endmodule