jishuqi.vhd

来自「2FSK调制功能」· VHDL 代码 · 共 56 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jishuqi is
   port(
clk: in std_logic;
din:in std_logic_vector(1 downto 0);
d:out std_logic_vector(5 downto 0)
 );
end jishuqi;
architecture a of jishuqi is
signal qn:std_logic_vector(9 downto 0);
begin
  process(clk)
    begin 
    if(clk'event and clk='1')then
      if(din="00")then
        if(qn="0000001111")then
           qn<= "0000010000";
        else
           qn<=qn+1;
        end if;
      elsif(din="01")then
       if(qn<="0011110000")then
          qn<="0011101111";
        else
           qn<=qn+1;
        end if;
     elsif(din="11")then
        if(qn<="0111110000")then
           qn<="0111101111";
        else
           qn<=qn+1;
        end if;
 
     elsif(din="10")then
       if(qn<="1111110000")then
          qn<="1111011111";
        else
           qn<=qn+1;
        end if;

        end if;
   end if;
end process;
d<=qn(9 downto 4);
end a;