📄 jishuqi.rpt
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# !din0 & din1 & d0 & d1 & d2 & d3 & d4 & d5 & !_LC040 & qn0;
-- Node name is '~1155~2'
-- Equation name is '~1155~2', location is LC048, type is buried.
-- synthesized logic cell
_LC048 = LCELL( _EQ044 $ GND);
_EQ044 = din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC044 & qn3
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC044 & qn2
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC044 & qn1
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC044 & qn0
# din0 & !din1 & d0 & d1 & d2 & d3 & !_LC052 & qn3;
-- Node name is '~1155~3'
-- Equation name is '~1155~3', location is LC037, type is buried.
-- synthesized logic cell
_LC037 = LCELL( _EQ045 $ GND);
_EQ045 = din0 & !din1 & d0 & d1 & d2 & d3 & !_LC052 & qn2
# din0 & !din1 & d0 & d1 & d2 & d3 & !_LC052 & qn1
# din0 & !din1 & d0 & d1 & d2 & d3 & !_LC052 & qn0
# din0 & din1 & d5 & !_LC044
# din0 & !din1 & d5 & !_LC052;
-- Node name is '~1161~1'
-- Equation name is '~1161~1', location is LC064, type is buried.
-- synthesized logic cell
_LC064 = LCELL( _EQ046 $ GND);
_EQ046 = d0 & d1 & d2 & d3 & d4 & d5 & !_LC036 & !_LC038 & !_LC039 &
!_LC042 & qn0
# !din0 & din1 & d0 & d1 & d2 & d3 & d4 & d5 & !_LC039 & qn3
# !din0 & din1 & d0 & d1 & d2 & d3 & d4 & d5 & !_LC039 & qn2
# !din0 & din1 & d0 & d1 & d2 & d3 & d4 & d5 & !_LC039 & qn1
# !din0 & din1 & d0 & d1 & d2 & d3 & d4 & d5 & !_LC039 & qn0;
-- Node name is '~1161~2'
-- Equation name is '~1161~2', location is LC063, type is buried.
-- synthesized logic cell
_LC063 = LCELL( _EQ047 $ GND);
_EQ047 = din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC036 & qn3
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC036 & qn2
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC036 & qn1
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC036 & qn0
# din0 & !din1 & d0 & d1 & d2 & d3 & !_LC038 & qn3;
-- Node name is '~1161~3'
-- Equation name is '~1161~3', location is LC056, type is buried.
-- synthesized logic cell
_LC056 = LCELL( _EQ048 $ GND);
_EQ048 = din0 & !din1 & d0 & d1 & d2 & d3 & !_LC038 & qn2
# din0 & !din1 & d0 & d1 & d2 & d3 & !_LC038 & qn1
# din0 & !din1 & d0 & d1 & d2 & d3 & !_LC038 & qn0
# din0 & din1 & d5 & !_LC036
# din0 & !din1 & d5 & !_LC038;
-- Node name is '~1167~1'
-- Equation name is '~1167~1', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ049 $ GND);
_EQ049 = din1 & d0 & d1 & d2 & d3 & d4 & !d5 & !_LC034 & qn2
# din1 & d0 & d1 & d2 & d3 & d4 & !d5 & !_LC034 & qn0
# din1 & d0 & d1 & d2 & d3 & d4 & !d5 & !_LC034 & qn1
# din1 & d0 & d1 & d2 & d3 & d4 & !d5 & !_LC034 & qn3
# !din0 & din1 & !_LC046;
-- Node name is '~1173~1'
-- Equation name is '~1173~1', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ050 $ GND);
_EQ050 = din0 & din1 & d0 & d1 & d2 & d3 & d4 & _LC018 & qn3
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & _LC018 & qn2
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & _LC018 & qn1
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & _LC018 & qn0
# din0 & !din1 & d0 & d1 & d2 & d3 & _LC025 & qn3;
-- Node name is '~1173~2'
-- Equation name is '~1173~2', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ051 $ GND);
_EQ051 = din0 & !din1 & d0 & d1 & d2 & d3 & _LC025 & qn2
# din0 & !din1 & d0 & d1 & d2 & d3 & _LC025 & qn1
# din0 & !din1 & d0 & d1 & d2 & d3 & _LC025 & qn0
# din1 & d5 & _LC018 & !qn0 & !qn1 & !qn2 & !qn3
# din0 & d5 & _LC018 & _LC025;
-- Node name is '~1173~3'
-- Equation name is '~1173~3', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ052 $ GND);
_EQ052 = din1 & !d4 & d5 & _LC018
# din1 & !d3 & d5 & _LC018
# din1 & !d2 & d5 & _LC018
# din1 & !d1 & d5 & _LC018
# din1 & !d0 & d5 & _LC018;
-- Node name is '~1173~4'
-- Equation name is '~1173~4', location is LC053, type is buried.
-- synthesized logic cell
_LC053 = LCELL( _EQ053 $ GND);
_EQ053 = !din0 & !d0 & !d1 & !d2 & !d3 & !d4 & !d5 & qn0 & qn1 & qn2 &
qn3
# !din0 & din1 & !qn0 & !qn1 & !qn2 & !qn3
# !din0 & din1 & !d5
# !din0 & din1 & !d4
# !din0 & din1 & !d3;
-- Node name is '~1179~1'
-- Equation name is '~1179~1', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ054 $ GND);
_EQ054 = din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC017 & qn2 &
!qn3
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC017 & qn0 &
!qn3
# din0 & din1 & d0 & d1 & d2 & d3 & d4 & !_LC017 & qn1 &
!qn3
# din0 & !din1 & d0 & d1 & d2 & d3 & !_LC026 & qn1 & !qn3
# din0 & !din1 & d0 & d1 & d2 & d3 & !_LC026 & qn0 & !qn3;
-- Node name is '~1179~2'
-- Equation name is '~1179~2', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ055 $ GND);
_EQ055 = din0 & !din1 & d0 & d1 & d2 & d3 & !_LC026 & qn2 & !qn3
# din0 & din1 & d5 & !_LC017 & !qn3
# din0 & !din1 & d4 & !_LC026 & !qn3
# din0 & !din1 & d5 & !_LC026 & !qn3
# !din0 & !din1 & !_LC028 & !qn3;
-- Node name is '~1179~3'
-- Equation name is '~1179~3', location is LC054, type is buried.
-- synthesized logic cell
_LC054 = LCELL( _EQ056 $ GND);
_EQ056 = din0 & !din1 & d0 & d1 & d2 & d3 & qn0 & qn1 & qn2 & qn3
# din0 & din1 & d5 & qn0 & qn1 & qn2 & qn3
# din0 & !din1 & d4 & qn0 & qn1 & qn2 & qn3
# din0 & !din1 & d5 & qn0 & qn1 & qn2 & qn3
# !din0 & !din1 & qn0 & qn1 & qn2 & qn3;
-- Node name is '~1185~1'
-- Equation name is '~1185~1', location is LC061, type is buried.
-- synthesized logic cell
_LC061 = LCELL( _EQ057 $ GND);
_EQ057 = din0 & d0 & d1 & d2 & d3 & d4 & qn0 & !qn1 & !qn2
# d0 & d1 & d2 & d3 & d4 & d5 & qn0 & !qn1 & !qn2
# d0 & d1 & d2 & d3 & d4 & d5 & !qn0 & qn1 & !qn2
# d0 & d1 & d2 & d3 & d4 & d5 & !qn0 & !qn2 & qn3
# !din1 & d0 & d1 & d2 & d3 & qn0 & qn1 & qn2;
-- Node name is '~1185~2'
-- Equation name is '~1185~2', location is LC062, type is buried.
-- synthesized logic cell
_LC062 = LCELL( _EQ058 $ GND);
_EQ058 = !din1 & d0 & d1 & d2 & d3 & qn0 & !qn1 & !qn2
# !din1 & d0 & d1 & d2 & d3 & !qn1 & !qn2 & qn3
# !din1 & d0 & d1 & d2 & d3 & !qn0 & qn1 & !qn2
# din0 & d5 & qn0 & qn1 & qn2
# !din1 & d4 & qn0 & qn1 & qn2;
-- Node name is '~1185~3'
-- Equation name is '~1185~3', location is LC045, type is buried.
-- synthesized logic cell
_LC045 = LCELL( _EQ059 $ GND);
_EQ059 = !din0 & !din1 & qn0 & qn1 & qn2
# din0 & d5 & !qn0 & !qn2
# din0 & d5 & !qn1 & !qn2
# !din1 & d4 & !qn1 & !qn2
# !din1 & d4 & !qn0 & !qn2;
-- Node name is '~1191~1'
-- Equation name is '~1191~1', location is LC055, type is buried.
-- synthesized logic cell
_LC055 = LCELL( _EQ060 $ GND);
_EQ060 = din0 & d0 & d1 & d2 & d3 & d4 & qn0 & qn1
# d0 & d1 & d2 & d3 & d4 & d5 & qn0 & qn1
# !din1 & d0 & d1 & d2 & d3 & qn0 & qn1
# din0 & d5 & qn0 & qn1
# !din1 & d4 & qn0 & qn1;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X015 occurs in LABs A, C, D
-- _X016 occurs in LABs A, D
-- _X021 occurs in LABs A, D
-- _X022 occurs in LABs A, D
Project Information e:\jia\jishuqi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,907K
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