📄 jishuqi.rpt
字号:
(32) 48 C SOFT s t 1 0 1 2 11 1 0 ~1155~2
(27) 37 C SOFT s t 1 0 1 2 10 1 0 ~1155~3
(41) 64 D SOFT s t 1 0 1 2 14 1 0 ~1161~1
- 63 D SOFT s t 1 0 1 2 11 1 0 ~1161~2
(38) 56 D SOFT s t 1 0 1 2 10 1 0 ~1161~3
- 31 B SOFT s t 1 0 1 2 12 1 0 ~1167~1
(13) 32 B SOFT s t 1 0 1 2 11 1 0 ~1173~1
- 22 B SOFT s t 1 0 1 2 11 1 0 ~1173~2
(17) 24 B SOFT s t 1 0 1 1 7 1 0 ~1173~3
(37) 53 D SOFT s t 1 0 1 2 10 2 0 ~1173~4
(14) 30 B SOFT s t 1 0 1 2 11 0 1 ~1179~1
(18) 21 B SOFT s t 1 0 1 2 11 0 1 ~1179~2
- 54 D SOFT s t 1 0 1 2 10 0 1 ~1179~3
- 61 D SOFT s t 1 0 1 2 10 0 1 ~1185~1
(40) 62 D SOFT s t 1 0 1 2 10 0 1 ~1185~2
- 45 C SOFT s t 1 0 1 2 5 0 1 ~1185~3
- 55 D SOFT s t 1 0 1 2 8 0 1 ~1191~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\jia\jishuqi.rpt
jishuqi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------- LC1 qn3
| +------- LC5 qn2
| | +----- LC2 qn1
| | | +--- LC3 ~1143~1
| | | | +- LC6 ~1149~1
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'A'
LC | | | | | | A B C D | Logic cells that feed LAB 'A':
LC1 -> * * * - * | * * * * | <-- qn3
LC5 -> * * * - * | * * * * | <-- qn2
LC2 -> * * * - * | * * * * | <-- qn1
Pin
43 -> - - - - - | - - - - | <-- clk
12 -> * * * * * | * * * * | <-- din0
11 -> * * * * * | * * * * | <-- din1
LC20 -> * * * - * | * * * * | <-- d0
LC19 -> * * * - * | * * * * | <-- d1
LC51 -> * * * - * | * * * * | <-- d2
LC35 -> * * * - * | * * * * | <-- d3
LC49 -> * * * * * | * * * * | <-- d4
LC33 -> * * * * * | * * * * | <-- d5
LC59 -> - - - * * | * - - - | <-- |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|cout_node
LC57 -> - - - * * | * - - - | <-- |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|cout_node
LC60 -> - - - * * | * - - - | <-- |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|cout_node
LC50 -> * * * - * | * * * * | <-- qn0
LC30 -> * - - - - | * - - - | <-- ~1179~1
LC21 -> * - - - - | * - - - | <-- ~1179~2
LC54 -> * - - - - | * - - - | <-- ~1179~3
LC61 -> - * - - - | * - - - | <-- ~1185~1
LC62 -> - * - - - | * - - - | <-- ~1185~2
LC45 -> - * - - - | * - - - | <-- ~1185~3
LC55 -> - - * - - | * - - - | <-- ~1191~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\jia\jishuqi.rpt
jishuqi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC20 d0
| +--------------------------- LC19 d1
| | +------------------------- LC28 |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|gcp2
| | | +----------------------- LC27 |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node4
| | | | +--------------------- LC26 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|gcp2
| | | | | +------------------- LC25 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node4
| | | | | | +----------------- LC17 |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|gcp2
| | | | | | | +--------------- LC18 |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node4
| | | | | | | | +------------- LC23 |LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node4
| | | | | | | | | +----------- LC31 ~1167~1
| | | | | | | | | | +--------- LC32 ~1173~1
| | | | | | | | | | | +------- LC22 ~1173~2
| | | | | | | | | | | | +----- LC24 ~1173~3
| | | | | | | | | | | | | +--- LC30 ~1179~1
| | | | | | | | | | | | | | +- LC21 ~1179~2
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC20 -> * * - * - * - * * * * * * * * | * * * * | <-- d0
LC19 -> * * - - - - - - - * * * * * * | * * * * | <-- d1
LC28 -> - - - - - - - - - - - - - - * | - * - - | <-- |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|gcp2
LC27 -> * - - - - - - - - - - - - - - | - * - - | <-- |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node4
LC26 -> - - - - - - - - - - - - - * * | - * - - | <-- |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|gcp2
LC25 -> * - - - - - - - - - * * - - - | - * - - | <-- |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node4
LC17 -> - - - - - - - - - - - - - * * | - * - - | <-- |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|gcp2
LC18 -> - - - - - - - - - - * * * - - | - * - - | <-- |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node4
LC23 -> * - - - - - - - - - - - - - - | - * - - | <-- |LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node4
LC31 -> - * - - - - - - - - - - - - - | - * - - | <-- ~1167~1
LC32 -> * - - - - - - - - - - - - - - | - * - - | <-- ~1173~1
LC22 -> * - - - - - - - - - - - - - - | - * - - | <-- ~1173~2
LC24 -> * - - - - - - - - - - - - - - | - * - - | <-- ~1173~3
Pin
43 -> - - - - - - - - - - - - - - - | - - - - | <-- clk
12 -> * * - - - - - - - * * * - * * | * * * * | <-- din0
11 -> * * - - - - - - - * * * * * * | * * * * | <-- din1
LC51 -> * * - - - - - - - * * * * * * | * * * * | <-- d2
LC35 -> - * - - - - - - - * * * * * * | * * * * | <-- d3
LC49 -> * * - - - - - - - * * - * * * | * * * * | <-- d4
LC33 -> * * - - - - - - - * - * * - * | * * * * | <-- d5
LC43 -> - * - - - - - - - - - - - - - | - * - - | <-- |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node5
LC41 -> - * - - - - - - - - - - - - - | - * - - | <-- |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node5
LC34 -> - * - - - - - - - * - - - - - | - * - - | <-- |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node5
LC46 -> - - - - - - - - - * - - - - - | - * - - | <-- |LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node5
LC1 -> - * - * - * - * * * * * - * * | * * * * | <-- qn3
LC5 -> - * * * * * * * * * * * - * * | * * * * | <-- qn2
LC2 -> - * * * * * * * * * * * - * - | * * * * | <-- qn1
LC50 -> - * * * * * * * * * * * - * - | * * * * | <-- qn0
LC53 -> * * - - - - - - - - - - - - - | - * - - | <-- ~1173~4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\jia\jishuqi.rpt
jishuqi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC35 d3
| +----------------------------- LC33 d5
| | +--------------------------- LC43 |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node5
| | | +------------------------- LC42 |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node6
| | | | +----------------------- LC41 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node5
| | | | | +--------------------- LC38 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node6
| | | | | | +------------------- LC34 |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node5
| | | | | | | +----------------- LC36 |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node6
| | | | | | | | +--------------- LC44 |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | +------------- LC46 |LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | +----------- LC39 |LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | | | +--------- LC40 |LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | | | | +------- LC47 ~1155~1
| | | | | | | | | | | | | +----- LC48 ~1155~2
| | | | | | | | | | | | | | +--- LC37 ~1155~3
| | | | | | | | | | | | | | | +- LC45 ~1185~3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC35 -> * * - - - - - - * - - * * * * - | * * * * | <-- d3
LC33 -> * * - - - - - - - - - - * - * * | * * * * | <-- d5
LC44 -> * - - - - - - - - - - - * * * - | - - * - | <-- |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node7
LC40 -> * - - - - - - - - - - - * - - - | - - * - | <-- |LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node7
LC47 -> * - - - - - - - - - - - - - - - | - - * - | <-- ~1155~1
LC48 -> * - - - - - - - - - - - - - - - | - - * - | <-- ~1155~2
LC37 -> * - - - - - - - - - - - - - - - | - - * - | <-- ~1155~3
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
12 -> * * - - - - - - - - - - * * * * | * * * * | <-- din0
11 -> * * - - - - - - - - - - * * * * | * * * * | <-- din1
LC20 -> * * * * * * * * * * * * * * * - | * * * * | <-- d0
LC19 -> * * * * * * * * * * * * * * * - | * * * * | <-- d1
LC51 -> * * - * - * - * * - * * * * * - | * * * * | <-- d2
LC49 -> * * - - - - - - - - - - * * - * | * * * * | <-- d4
LC58 -> * - - - - - - - - - - - * - - - | - - * - | <-- |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node7
LC52 -> * - - - - - - - - - - - * * * - | - - * - | <-- |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node7
LC1 -> * * * * * * * * * * * * * * - - | * * * * | <-- qn3
LC5 -> * * * * * * * * * * * * * * * * | * * * * | <-- qn2
LC2 -> * * * * * * * * * * * * * * * * | * * * * | <-- qn1
LC50 -> * * * * * * * * * * * * * * * * | * * * * | <-- qn0
LC3 -> - * - - - - - - - - - - - - - - | - - * - | <-- ~1143~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\jia\jishuqi.rpt
jishuqi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC51 d2
| +----------------------------- LC49 d4
| | +--------------------------- LC59 |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|cout_node
| | | +------------------------- LC58 |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node7
| | | | +----------------------- LC57 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|cout_node
| | | | | +--------------------- LC52 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node7
| | | | | | +------------------- LC60 |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|cout_node
| | | | | | | +----------------- LC50 qn0
| | | | | | | | +--------------- LC64 ~1161~1
| | | | | | | | | +------------- LC63 ~1161~2
| | | | | | | | | | +----------- LC56 ~1161~3
| | | | | | | | | | | +--------- LC53 ~1173~4
| | | | | | | | | | | | +------- LC54 ~1179~3
| | | | | | | | | | | | | +----- LC61 ~1185~1
| | | | | | | | | | | | | | +--- LC62 ~1185~2
| | | | | | | | | | | | | | | +- LC55 ~1191~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC51 -> * * * * * * * * * * * * * * * * | * * * * | <-- d2
LC49 -> * * - - - - - * * * - * * * * * | * * * * | <-- d4
LC50 -> * * * * * * * * * * * * * * * * | * * * * | <-- qn0
LC64 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~1161~1
LC63 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~1161~2
LC56 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~1161~3
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
12 -> * * - - - - - * * * * * * * * * | * * * * | <-- din0
11 -> * * - - - - - * * * * * * * * * | * * * * | <-- din1
LC20 -> * * * * * * * * * * * * * * * * | * * * * | <-- d0
LC19 -> * * * * * * * * * * * * * * * * | * * * * | <-- d1
LC35 -> * * * * * * * * * * * * * * * * | * * * * | <-- d3
LC33 -> * * - - - - - * * - * * * * * * | * * * * | <-- d5
LC42 -> * - - - - - - - * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node6
LC38 -> * - - - - - - - * * * - - - - - | - - - * | <-- |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node6
LC36 -> * - - - - - - - * * * - - - - - | - - - * | <-- |LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node6
LC39 -> * - - - - - - - * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node6
LC1 -> * * * * * * * - * * - * * * * - | * * * * | <-- qn3
LC5 -> * * * * * * * - * * * * * * * - | * * * * | <-- qn2
LC2 -> * * * * * * * - * * * * * * * * | * * * * | <-- qn1
LC6 -> - * - - - - - - - - - - - - - - | - - - * | <-- ~1149~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\jia\jishuqi.rpt
jishuqi
** EQUATIONS **
clk : INPUT;
din0 : INPUT;
din1 : INPUT;
-- Node name is 'd0' = 'qn4'
-- Equation name is 'd0', location is LC020, type is output.
d0 = DFFE( _EQ001 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC022 & !_LC024 & !_LC032 & !_LC053 & _X001 & _X002 & _X003 &
_X004 & _X005 & _X006 & _X007;
_X001 = EXP(!din0 & !din1 & _LC027);
_X002 = EXP(!din0 & din1 & !d2);
_X003 = EXP(!din0 & din1 & _LC023);
_X004 = EXP( din0 & !din1 & d4 & _LC025);
_X005 = EXP( din0 & !din1 & d5 & _LC025);
_X006 = EXP(!din0 & din1 & !d0);
_X007 = EXP(!din0 & din1 & !d1);
-- Node name is 'd1' = 'qn5'
-- Equation name is 'd1', location is LC019, type is output.
d1 = DFFE( _EQ002 $ _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = din0 & !din1 & d0 & d1 & d2 & d3 & !_LC041 & _X008
# din0 & din1 & d5 & !_LC034
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -