da.vhd

2FSK调制功能

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity DA is
   port(
clk:in std_logic;
wr,cs,sel :out std_logic
);
end DA;
architecture a of DA is
begin
cs<='0';
sel<='0';
process(clk)
  variable dd:std_logic_vector(1 downto 0);

  begin
  if (clk'event and clk='1') then
    if dd="11" then
       dd:="00";
    else
      dd:=dd+1;
    end if;
 

  if dd="01" then
      wr<='1';
  elsif dd="10" then
      wr<='0';
  elsif dd="11" then
      wr<='0';
  elsif dd="00" then
      wr<='1';
  end if;

end if;

end process;


    

--wr<='1' when dd="00" else
--    '1' when dd="01" else
--    '0' when dd="10" else
--    '0' ;
    
end a;