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📄 shift.rpt

📁 2FSK调制功能
💻 RPT
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\jia\shift.rpt
shift

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                         Logic cells placed in LAB 'B'
        +------------------------------- LC17 do0
        | +----------------------------- LC27 do1
        | | +--------------------------- LC24 |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node3
        | | | +------------------------- LC23 |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node4
        | | | | +----------------------- LC22 |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node5
        | | | | | +--------------------- LC21 |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node6
        | | | | | | +------------------- LC19 |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node7
        | | | | | | | +----------------- LC18 |LPM_ADD_SUB:129|addcore:adder|addcore:adder1|result_node0
        | | | | | | | | +--------------- LC25 |LPM_ADD_SUB:129|addcore:adder|addcore:adder1|result_node1
        | | | | | | | | | +------------- LC26 clkout19
        | | | | | | | | | | +----------- LC20 clkout18
        | | | | | | | | | | | +--------- LC32 clkout17
        | | | | | | | | | | | | +------- LC31 clkout16
        | | | | | | | | | | | | | +----- LC30 clkout15
        | | | | | | | | | | | | | | +--- LC29 clkout14
        | | | | | | | | | | | | | | | +- LC28 clkout13
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> * * - - - - - - - - - - - - - - | - * | <-- do0
LC24 -> - - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node3
LC23 -> - - - - - - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node4
LC22 -> - - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node5
LC21 -> - - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node6
LC19 -> - - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node7
LC18 -> - - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:129|addcore:adder|addcore:adder1|result_node0
LC25 -> - - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:129|addcore:adder|addcore:adder1|result_node1
LC26 -> * * - - - - - - * * * * * * * * | - * | <-- clkout19
LC20 -> * * - - - - - * * * * * * * * * | - * | <-- clkout18
LC32 -> * * - - - - * * * * * * * * * * | - * | <-- clkout17
LC31 -> * * - - - * * * * * * * * * * * | - * | <-- clkout16
LC30 -> * * - - * * * * * * * * * * * * | - * | <-- clkout15
LC29 -> * * - * * * * * * * * * * * * * | - * | <-- clkout14
LC28 -> * * * * * * * * * * * * * * * * | - * | <-- clkout13

Pin
43   -> - - - - - - - - - - - - - - - - | - - | <-- clk
LC4  -> * * * * * * * * * * * * * * * * | - * | <-- clkout12
LC2  -> * * * * * * * * * * * * * * * * | * * | <-- clkout11
LC1  -> * * * * * * * * * * * * * * * * | * * | <-- clkout10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\jia\shift.rpt
shift

** EQUATIONS **

clk      : INPUT;

-- Node name is ':13' = 'clkout10' 
-- Equation name is 'clkout10', location is LC001, type is buried.
clkout10 = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':12' = 'clkout11' 
-- Equation name is 'clkout11', location is LC002, type is buried.
clkout11 = TFFE( clkout10, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':11' = 'clkout12' 
-- Equation name is 'clkout12', location is LC004, type is buried.
clkout12 = TFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  clkout10 &  clkout11;

-- Node name is ':10' = 'clkout13' 
-- Equation name is 'clkout13', location is LC028, type is buried.
clkout13 = DFFE( _EQ002 $  _LC024, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18 &  clkout19 & 
              _LC024;

-- Node name is ':9' = 'clkout14' 
-- Equation name is 'clkout14', location is LC029, type is buried.
clkout14 = DFFE( _EQ003 $  _LC023, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18 &  clkout19 & 
              _LC023;

-- Node name is ':8' = 'clkout15' 
-- Equation name is 'clkout15', location is LC030, type is buried.
clkout15 = DFFE( _EQ004 $  _LC022, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18 &  clkout19 & 
              _LC022;

-- Node name is ':7' = 'clkout16' 
-- Equation name is 'clkout16', location is LC031, type is buried.
clkout16 = DFFE( _EQ005 $  _LC021, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18 &  clkout19 & 
              _LC021;

-- Node name is ':6' = 'clkout17' 
-- Equation name is 'clkout17', location is LC032, type is buried.
clkout17 = DFFE( _EQ006 $  _LC019, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18 &  clkout19 & 
              _LC019;

-- Node name is ':5' = 'clkout18' 
-- Equation name is 'clkout18', location is LC020, type is buried.
clkout18 = DFFE( _EQ007 $  _LC018, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18 &  clkout19 & 
              _LC018;

-- Node name is ':4' = 'clkout19' 
-- Equation name is 'clkout19', location is LC026, type is buried.
clkout19 = DFFE( _EQ008 $  _LC025, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18 &  clkout19 & 
              _LC025;

-- Node name is 'do0' = 'a0' 
-- Equation name is 'do0', location is LC017, type is output.
 do0     = TFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18 &  clkout19;

-- Node name is 'do1' = 'a1' 
-- Equation name is 'do1', location is LC027, type is output.
 do1     = TFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18 &  clkout19 &  do0;

-- Node name is '|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( clkout13 $  _EQ011);
  _EQ011 =  clkout10 &  clkout11 &  clkout12;

-- Node name is '|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( clkout14 $  _EQ012);
  _EQ012 =  clkout10 &  clkout11 &  clkout12 &  clkout13;

-- Node name is '|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried 
_LC022   = LCELL( clkout15 $  _EQ013);
  _EQ013 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14;

-- Node name is '|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried 
_LC021   = LCELL( clkout16 $  _EQ014);
  _EQ014 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15;

-- Node name is '|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried 
_LC019   = LCELL( clkout17 $  _EQ015);
  _EQ015 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16;

-- Node name is '|LPM_ADD_SUB:129|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC018', type is buried 
_LC018   = LCELL( clkout18 $  _EQ016);
  _EQ016 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17;

-- Node name is '|LPM_ADD_SUB:129|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( clkout19 $  _EQ017);
  _EQ017 =  clkout10 &  clkout11 &  clkout12 &  clkout13 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  clkout18;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                           e:\jia\shift.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 7,423K

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