📄 cunchuqi.rpt
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LC29 -> - - - * - - - - - - - - - - - - | - * | <-- ~3950~1
LC22 -> - - * - - - - - - - - - - - - - | - * | <-- ~3974~1
LC23 -> - - * - - - - - - - - - - - - - | - * | <-- ~3974~2
LC24 -> - - * - - - - - - - - - - - - - | - * | <-- ~3974~3
LC25 -> - * - - - - - - - - - - - - - - | - * | <-- ~3980~1
LC27 -> - * - - - - - - - - - - - - - - | - * | <-- ~3980~2
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
6 -> * * * * * * * * * * * * * * * * | * * | <-- d0
8 -> * * * * * * * * * * * * * * * * | * * | <-- d1
9 -> * * * * * * * * * * * * * * * * | * * | <-- d2
11 -> * * * * * * * * * * * * * * * * | * * | <-- d3
5 -> * * * * * * * * * * * * * * * * | * * | <-- d4
4 -> - * * * * * * * * * * * * * * * | * * | <-- d5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\jia\cunchuqi.rpt
cunchuqi
** EQUATIONS **
clk : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
-- Node name is 'wave0' = 'wave0~58'
-- Equation name is 'wave0', location is LC028, type is output.
wave0 = DFFE( _EQ001 $ _EQ002, GLOBAL(!clk), VCC, VCC, VCC);
_EQ001 = d0 & !d1 & d3 & d4 & _X001 & _X002
# !d0 & d1 & d3 & d4 & _X001 & _X002
# !d0 & !d1 & d2 & !d3 & _X001 & _X002
# !d0 & !d2 & !d3 & d4 & _X001 & _X002;
_X001 = EXP( d1 & !d3 & !d4);
_X002 = EXP(!d0 & d2 & d3);
_EQ002 = _X001 & _X002;
_X001 = EXP( d1 & !d3 & !d4);
_X002 = EXP(!d0 & d2 & d3);
-- Node name is 'wave1' = 'wave1~58'
-- Equation name is 'wave1', location is LC031, type is output.
wave1 = DFFE( _EQ003 $ _EQ004, GLOBAL(!clk), VCC, VCC, VCC);
_EQ003 = !d0 & d1 & d2 & !d3 & d5 & !_LC025 & !_LC027
# !d1 & !d2 & !d3 & d4 & d5 & !_LC025 & !_LC027
# !d0 & d1 & !d2 & !d4 & !d5 & !_LC025 & !_LC027
# d1 & d2 & !d3 & d4 & !_LC025 & !_LC027;
_EQ004 = !_LC025 & !_LC027;
-- Node name is 'wave2' = 'wave2~58'
-- Equation name is 'wave2', location is LC032, type is output.
wave2 = DFFE( _EQ005 $ _EQ006, GLOBAL(!clk), VCC, VCC, VCC);
_EQ005 = d0 & d2 & d3 & d4 & d5 & !_LC022 & !_LC023 & !_LC024
# d0 & d1 & d2 & d3 & d5 & !_LC022 & !_LC023 & !_LC024
# d0 & d1 & d2 & !d3 & !d5 & !_LC022 & !_LC023 & !_LC024
# !d0 & d1 & d2 & !d4 & d5 & !_LC022 & !_LC023 & !_LC024;
_EQ006 = !_LC022 & !_LC023 & !_LC024;
-- Node name is 'wave3' = 'wave3~58'
-- Equation name is 'wave3', location is LC011, type is output.
wave3 = DFFE( _EQ007 $ d5, GLOBAL(!clk), VCC, VCC, VCC);
_EQ007 = !_LC020 & !_LC021 & _X003;
_X003 = EXP(!d0 & !d1 & d2);
-- Node name is 'wave4' = 'wave4~58'
-- Equation name is 'wave4', location is LC010, type is output.
wave4 = DFFE( _EQ008 $ _EQ009, GLOBAL(!clk), VCC, VCC, VCC);
_EQ008 = d0 & d1 & !d2 & d3 & !d4 & !_LC018 & !_LC019
# !d0 & d1 & d2 & !d3 & !d5 & !_LC018 & !_LC019
# !d0 & d1 & !d2 & !d3 & d5 & !_LC018 & !_LC019
# !d0 & d1 & !d2 & d3 & !d5 & !_LC018 & !_LC019;
_EQ009 = !_LC018 & !_LC019;
-- Node name is 'wave5' = 'wave5~58'
-- Equation name is 'wave5', location is LC008, type is output.
wave5 = DFFE( _EQ010 $ !d5, GLOBAL(!clk), VCC, VCC, VCC);
_EQ010 = !_LC017 & _X004;
_X004 = EXP(!d3 & d4);
-- Node name is 'wave6' = 'wave6~58'
-- Equation name is 'wave6', location is LC030, type is output.
wave6 = DFFE( _EQ011 $ _EQ012, GLOBAL(!clk), VCC, VCC, VCC);
_EQ011 = d0 & d1 & d3 & d4 & !d5 & !_LC029 & _X005
# d1 & !d2 & !d3 & !d4 & !d5 & !_LC029 & _X005
# d0 & !d2 & !d3 & !d4 & !d5 & !_LC029 & _X005
# !d1 & d2 & !d3 & !d4 & !d5 & !_LC029 & _X005;
_X005 = EXP( d3 & !d4 & d5);
_EQ012 = !_LC029 & _X005;
_X005 = EXP( d3 & !d4 & d5);
-- Node name is 'wave7' = 'wave7~58'
-- Equation name is 'wave7', location is LC026, type is output.
wave7 = DFFE( _EQ013 $ !d5, GLOBAL(!clk), VCC, VCC, VCC);
_EQ013 = !d0 & !d1 & !d2 & !d3 & !d4 & !d5;
-- Node name is '~3950~1'
-- Equation name is '~3950~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ014 $ GND);
_EQ014 = d1 & d2 & !d4 & d5
# d2 & d3 & d4 & !d5
# !d1 & !d2 & d4 & d5
# !d0 & !d2 & d4 & d5
# !d3 & d4 & d5;
-- Node name is '~3956~1'
-- Equation name is '~3956~1', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ015 $ GND);
_EQ015 = !d0 & !d1 & !d2 & !d3 & !d4 & !d5
# d0 & d1 & !d2
# d0 & d3 & !d4
# d1 & d3 & !d4
# !d1 & d2;
-- Node name is '~3962~1'
-- Equation name is '~3962~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ016 $ GND);
_EQ016 = d0 & d2 & !d4 & d5
# d0 & !d2 & d4 & d5
# d0 & d2 & d4 & !d5
# !d0 & d2 & d3 & d5
# !d1 & !d3 & d4 & d5;
-- Node name is '~3962~2'
-- Equation name is '~3962~2', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ017 $ GND);
_EQ017 = !d0 & !d1 & d3 & d5
# !d1 & d2 & !d4 & d5
# d0 & !d2 & !d4 & !d5;
-- Node name is '~3968~1'
-- Equation name is '~3968~1', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ018 $ GND);
_EQ018 = d0 & d1 & !d2 & d3 & !d4 & d5
# !d0 & !d1 & !d2 & !d3 & !d4 & d5
# !d0 & d1 & !d2 & d3 & d4
# !d1 & d2 & d3 & d4 & !d5
# !d0 & d2 & !d3 & !d4 & d5;
-- Node name is '~3968~2'
-- Equation name is '~3968~2', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ019 $ GND);
_EQ019 = d1 & d2 & !d3 & !d4 & !d5
# !d1 & d2 & d4 & d5
# d0 & d1 & d2 & !d3
# d0 & !d1 & !d2 & d3
# d0 & d1 & !d3 & !d4;
-- Node name is '~3974~1'
-- Equation name is '~3974~1', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ020 $ GND);
_EQ020 = !d0 & d1 & !d2 & d4 & d5
# !d0 & d2 & d3 & d4 & !d5
# !d0 & d2 & d3 & !d4 & d5
# d0 & !d1 & !d2 & !d3 & d5
# d0 & !d2 & !d3 & !d4 & d5;
-- Node name is '~3974~2'
-- Equation name is '~3974~2', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ021 $ GND);
_EQ021 = !d0 & !d1 & !d3 & d4 & d5
# !d0 & d1 & !d2 & !d4 & !d5
# !d1 & d2 & !d3 & !d4 & !d5
# d0 & d1 & d3 & d4
# d0 & d1 & d4 & !d5;
-- Node name is '~3974~3'
-- Equation name is '~3974~3', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ022 $ GND);
_EQ022 = d1 & d2 & d4 & !d5
# d0 & !d1 & !d3 & !d4
# d0 & !d1 & !d4 & !d5
# !d1 & !d2 & d3 & !d5;
-- Node name is '~3980~1'
-- Equation name is '~3980~1', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ023 $ GND);
_EQ023 = d0 & d2 & d3 & !d4
# d1 & !d3 & d4 & !d5
# d0 & !d2 & !d3 & d4
# !d0 & d2 & d3 & !d5
# !d0 & !d2 & d3 & d5;
-- Node name is '~3980~2'
-- Equation name is '~3980~2', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ024 $ GND);
_EQ024 = d0 & !d1 & d3 & !d4
# d0 & d1 & !d3 & !d5
# !d0 & !d1 & d2 & !d5
# !d1 & d3 & !d5;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\jia\cunchuqi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,761K
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