📄 zuhe.rpt
字号:
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\jia\zuhe.rpt
zuhe
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 0/ 8( 0%) 3/16( 18%) 6/36( 16%)
B: LC17 - LC32 4/16( 25%) 1/ 8( 12%) 16/16(100%) 20/36( 55%)
C: LC33 - LC48 14/16( 87%) 1/ 8( 12%) 16/16(100%) 29/36( 80%)
D: LC49 - LC64 16/16(100%) 0/ 8( 0%) 0/16( 0%) 23/36( 63%)
E: LC65 - LC80 16/16(100%) 0/ 8( 0%) 16/16(100%) 26/36( 72%)
F: LC81 - LC96 16/16(100%) 4/ 8( 50%) 16/16(100%) 23/36( 63%)
G: LC97 - LC112 14/16( 87%) 6/ 8( 75%) 16/16(100%) 22/36( 61%)
H: LC113 - LC128 16/16(100%) 3/ 8( 37%) 16/16(100%) 21/36( 58%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 15/64 ( 23%)
Total logic cells used: 99/128 ( 77%)
Total shareable expanders used: 63/128 ( 49%)
Total Turbo logic cells used: 99/128 ( 77%)
Total shareable expanders not available (n/a): 36/128 ( 28%)
Average fan-in: 8.75
Total fan-in: 867
Total input pins required: 1
Total fast input logic cells required: 0
Total output pins required: 11
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 99
Total flipflops required: 38
Total product terms required: 372
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 60
Synthesized logic cells: 28/ 128 ( 21%)
Device-Specific Information: e:\jia\zuhe.rpt
zuhe
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\jia\zuhe.rpt
zuhe
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
79 125 H OUTPUT t 0 0 0 0 0 0 0 cs
58 91 F OUTPUT t 0 0 0 0 0 0 0 sel
75 118 H FF t 4 0 1 0 6 0 0 wave0 (|CUNCHUQI:15|:23)
74 117 H FF t 6 0 1 0 8 0 0 wave1 (|CUNCHUQI:15|:22)
70 109 G FF t 5 3 0 0 9 0 0 wave2 (|CUNCHUQI:15|:21)
69 107 G OUTPUT t 0 0 0 0 1 0 0 wave3 (|CUNCHUQI:15|:20)
68 105 G FF t 4 2 0 0 8 0 0 wave4 (|CUNCHUQI:15|:19)
64 99 G FF t 6 1 0 0 7 0 0 wave5 (|CUNCHUQI:15|:18)
65 101 G FF t 2 0 0 0 7 0 0 wave6 (|CUNCHUQI:15|:17)
61 94 F FF t 0 0 0 0 7 0 0 wave7 (|CUNCHUQI:15|:16)
60 93 F FF + t 0 0 0 0 2 0 0 wr
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\jia\zuhe.rpt
zuhe
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(22) 17 B DFFE s t r 6 0 0 0 8 1 0 |CUNCHUQI:15|wave3~58~fit~in1 (|CUNCHUQI:15|:20)
- 44 C SOFT s t 1 0 1 0 6 1 0 |CUNCHUQI:15|~3950~1
- 47 C SOFT s t 1 0 1 0 6 1 0 |CUNCHUQI:15|~3962~1
(18) 24 B SOFT s t 1 0 1 0 6 0 1 |CUNCHUQI:15|~3968~1
(5) 14 A SOFT s t 1 0 1 0 6 1 0 |CUNCHUQI:15|~3974~1
(4) 16 A SOFT s t 1 0 1 0 6 1 0 |CUNCHUQI:15|~3974~2
- 9 A SOFT s t 1 0 1 0 6 1 0 |CUNCHUQI:15|~3980~1
- 84 F TFFE + t 0 0 0 0 1 1 0 |DA:3|dd1 (|DA:3|:6)
- 106 G TFFE + t 0 0 0 0 0 1 1 |DA:3|dd0 (|DA:3|:7)
(71) 112 G TFFE + t 0 0 0 0 2 0 14 |FENPINQI:4|clkout12 (|FENPINQI:4|:4)
- 108 G TFFE + t 0 0 0 0 1 7 12 |FENPINQI:4|clkout11 (|FENPINQI:4|:5)
- 110 G TFFE + t 0 0 0 0 0 0 2 |FENPINQI:4|clkout10 (|FENPINQI:4|:6)
(73) 115 H SOFT t 0 0 0 0 8 0 2 |JISHUQI:23|LPM_ADD_SUB:214|addcore:adder|addcore:adder0|cout_node
(45) 67 E SOFT t 0 0 0 0 3 0 1 |JISHUQI:23|LPM_ADD_SUB:214|addcore:adder|addcore:adder0|gcp2
- 68 E SOFT t 0 0 0 0 5 0 1 |JISHUQI:23|LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node4
(46) 69 E SOFT t 0 0 0 0 6 0 1 |JISHUQI:23|LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node5
(76) 120 H SOFT t 0 0 0 0 7 0 2 |JISHUQI:23|LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node6
(77) 123 H SOFT t 0 0 0 0 8 0 2 |JISHUQI:23|LPM_ADD_SUB:214|addcore:adder|addcore:adder0|result_node7
(80) 126 H SOFT t 0 0 0 0 8 0 2 |JISHUQI:23|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|cout_node
- 111 G SOFT t 0 0 0 0 3 0 2 |JISHUQI:23|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|gcp2
- 70 E SOFT t 0 0 0 0 5 0 3 |JISHUQI:23|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node4
(50) 75 E SOFT t 0 0 0 0 6 0 1 |JISHUQI:23|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node5
- 127 H SOFT t 0 0 0 0 7 0 3 |JISHUQI:23|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node6
(81) 128 H SOFT t 0 0 0 0 8 0 3 |JISHUQI:23|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node7
- 116 H SOFT t 0 0 0 0 8 0 2 |JISHUQI:23|LPM_ADD_SUB:646|addcore:adder|addcore:adder0|cout_node
- 100 G SOFT t 0 0 0 0 3 0 2 |JISHUQI:23|LPM_ADD_SUB:646|addcore:adder|addcore:adder0|gcp2
- 66 E SOFT t 0 0 0 0 5 0 3 |JISHUQI:23|LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node4
- 78 E SOFT t 0 0 0 0 6 0 2 |JISHUQI:23|LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node5
- 119 H SOFT t 0 0 0 0 7 0 4 |JISHUQI:23|LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node6
- 122 H SOFT t 0 0 0 0 8 0 4 |JISHUQI:23|LPM_ADD_SUB:646|addcore:adder|addcore:adder0|result_node7
(63) 97 G SOFT t 0 0 0 0 3 0 1 |JISHUQI:23|LPM_ADD_SUB:862|addcore:adder|addcore:adder0|gcp2
(48) 72 E SOFT t 0 0 0 0 5 0 1 |JISHUQI:23|LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node4
(49) 73 E SOFT t 0 0 0 0 6 0 1 |JISHUQI:23|LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node5
- 82 F SOFT t 0 0 0 0 7 0 3 |JISHUQI:23|LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node6
- 121 H SOFT t 0 0 0 0 8 0 3 |JISHUQI:23|LPM_ADD_SUB:862|addcore:adder|addcore:adder0|result_node7
- 34 C DFFE t 4 1 0 0 14 6 37 |JISHUQI:23|qn9 (|JISHUQI:23|:10)
- 33 C DFFE t 4 2 0 0 14 7 34 |JISHUQI:23|qn8 (|JISHUQI:23|:11)
- 113 H DFFE t 4 0 1 0 20 7 42 |JISHUQI:23|qn7 (|JISHUQI:23|:12)
- 81 F DFFE t 4 0 1 0 20 7 47 |JISHUQI:23|qn6 (|JISHUQI:23|:13)
- 76 E DFFE t 7 4 1 0 18 7 51 |JISHUQI:23|qn5 (|JISHUQI:23|:14)
(44) 65 E DFFE t 7 3 0 0 15 6 55 |JISHUQI:23|qn4 (|JISHUQI:23|:15)
- 22 B DFFE t 5 2 1 0 16 0 44 |JISHUQI:23|qn3 (|JISHUQI:23|:16)
(17) 25 B DFFE t 4 0 1 0 16 0 49 |JISHUQI:23|qn2 (|JISHUQI:23|:17)
- 41 C DFFE t 3 0 1 0 15 0 49 |JISHUQI:23|qn1 (|JISHUQI:23|:18)
- 89 F DFFE t 3 0 1 0 10 0 51 |JISHUQI:23|qn0 (|JISHUQI:23|:19)
- 102 G SOFT s t 1 0 1 0 7 0 1 |JISHUQI:23|~1143~1
- 98 G SOFT s t 1 0 1 0 15 0 1 |JISHUQI:23|~1149~1
- 114 H SOFT s t 1 0 1 0 16 0 1 |JISHUQI:23|~1155~1
(24) 46 C SOFT s t 1 0 1 0 14 0 1 |JISHUQI:23|~1155~2
- 124 H SOFT s t 1 0 1 0 13 0 1 |JISHUQI:23|~1155~3
- 95 F SOFT s t 1 0 1 0 16 0 1 |JISHUQI:23|~1161~1
- 92 F SOFT s t 1 0 1 0 14 0 1 |JISHUQI:23|~1161~2
- 90 F SOFT s t 1 0 1 0 13 0 1 |JISHUQI:23|~1161~3
- 74 E SOFT s t 1 0 1 0 14 0 1 |JISHUQI:23|~1167~1
- 87 F SOFT s t 1 0 1 0 12 0 2 |JISHUQI:23|~1173~1
(52) 80 E SOFT s t 1 0 1 0 13 0 1 |JISHUQI:23|~1173~2
(51) 77 E SOFT s t 1 0 1 0 13 0 1 |JISHUQI:23|~1173~3
- 71 E SOFT s t 1 0 1 0 8 0 1 |JISHUQI:23|~1173~4
(29) 38 C SOFT s t 1 0 1 0 15 0 1 |JISHUQI:23|~1179~1
(31) 35 C SOFT s t 1 0 1 0 13 0 1 |JISHUQI:23|~1179~2
(57) 88 F SOFT s t 1 0 1 0 13 0 1 |JISHUQI:23|~1179~3
(56) 86 F SOFT s t 1 0 1 0 11 0 1 |JISHUQI:23|~1185~1
(55) 85 F SOFT s t 1 0 1 0 11 0 1 |JISHUQI:23|~1185~2
- 79 E SOFT s t 1 0 1 0 7 0 1 |JISHUQI:23|~1185~3
(54) 83 F SOFT s t 1 0 1 0 12 0 1 |JISHUQI:23|~1191~1
(62) 96 F SOFT s t 1 0 1 0 10 0 1 |JISHUQI:23|~1191~2
(36) 57 D SOFT t 0 0 0 0 2 0 2 |SHIFT:25|LPM_ADD_SUB:84|addcore:adder|addcore:adder0|result_node1
- 42 C SOFT t 0 0 0 0 4 0 1 |SHIFT:25|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node3
(28) 40 C SOFT t 0 0 0 0 5 0 1 |SHIFT:25|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node4
- 39 C SOFT t 0 0 0 0 6 0 1 |SHIFT:25|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node5
(33) 64 D SOFT t 0 0 0 0 7 0 1 |SHIFT:25|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node6
(37) 56 D SOFT t 0 0 0 0 8 0 1 |SHIFT:25|LPM_ADD_SUB:129|addcore:adder|addcore:adder0|result_node7
- 55 D SOFT t 0 0 0 0 9 0 1 |SHIFT:25|LPM_ADD_SUB:129|addcore:adder|addcore:adder1|result_node0
- 54 D SOFT t 0 0 0 0 10 0 1 |SHIFT:25|LPM_ADD_SUB:129|addcore:adder|addcore:adder1|result_node1
(40) 51 D TFFE t 0 0 0 0 13 0 31 |SHIFT:25|:2
- 50 D TFFE t 0 0 0 0 13 0 31 |SHIFT:25|:4
- 58 D DFFE t 0 0 0 0 12 0 12 |SHIFT:25|clkout19 (|SHIFT:25|:6)
(35) 59 D DFFE t 0 0 0 0 12 0 13 |SHIFT:25|clkout18 (|SHIFT:25|:7)
- 60 D DFFE t 0 0 0 0 12 0 14 |SHIFT:25|clkout17 (|SHIFT:25|:8)
(34) 61 D DFFE t 0 0 0 0 12 0 15 |SHIFT:25|clkout16 (|SHIFT:25|:9)
(41) 49 D DFFE t 0 0 0 0 12 0 16 |SHIFT:25|clkout15 (|SHIFT:25|:10)
- 52 D DFFE t 0 0 0 0 12 0 17 |SHIFT:25|clkout14 (|SHIFT:25|:11)
(39) 53 D DFFE t 0 0 0 0 12 0 18 |SHIFT:25|clkout13 (|SHIFT:25|:12)
(27) 43 C TFFE t 0 0 0 0 3 0 18 |SHIFT:25|clkout12 (|SHIFT:25|:13)
- 36 C TFFE t 0 0 0 0 2 0 19 |SHIFT:25|clkout11 (|SHIFT:25|:14)
(30) 37 C TFFE t 0 0 0 0 1 0 20 |SHIFT:25|clkout10 (|SHIFT:25|:15)
- 62 D TFFE t 0 0 0 0 13 0 2 |SHIFT:25|a1 (|SHIFT:25|:16)
- 63 D TFFE t 0 0 0 0 11 0 2 |SHIFT:25|a0 (|SHIFT:25|:17)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\jia\zuhe.rpt
zuhe
** LOGIC CELL INTERCONNECTIONS **
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