fenpinqi.rpt

2FSK调制功能

Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               e:\jia\fenpinqi.rpt
fenpinqi

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                   Logic cells placed in LAB 'B'
        +------------------------- LC17 clkout2
        | +----------------------- LC18 clkout4
        | | +--------------------- LC19 |LPM_ADD_SUB:94|addcore:adder|result_node3
        | | | +------------------- LC20 |LPM_ADD_SUB:94|addcore:adder|result_node4
        | | | | +----------------- LC21 |LPM_ADD_SUB:94|addcore:adder|result_node5
        | | | | | +--------------- LC22 |LPM_ADD_SUB:94|addcore:adder|result_node6
        | | | | | | +------------- LC23 |LPM_ADD_SUB:94|addcore:adder|result_node7
        | | | | | | | +----------- LC29 clkout17
        | | | | | | | | +--------- LC28 clkout16
        | | | | | | | | | +------- LC27 clkout15
        | | | | | | | | | | +----- LC26 clkout14
        | | | | | | | | | | | +--- LC25 clkout12
        | | | | | | | | | | | | +- LC24 clkout10
        | | | | | | | | | | | | | 
        | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> * - * * * * * * * * * - - | - * | <-- clkout2
LC18 -> * * * * * * * * * * * * - | - * | <-- clkout4
LC19 -> * - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:94|addcore:adder|result_node3
LC20 -> - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:94|addcore:adder|result_node4
LC21 -> - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:94|addcore:adder|result_node5
LC22 -> - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:94|addcore:adder|result_node6
LC23 -> - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:94|addcore:adder|result_node7
LC29 -> * - - - - - * * * * * - - | - * | <-- clkout17
LC28 -> * - - - - * * * * * * - - | - * | <-- clkout16
LC27 -> * - - - * * * * * * * - - | - * | <-- clkout15
LC26 -> * - - * * * * * * * * - - | - * | <-- clkout14
LC25 -> * - * * * * * * * * * * - | - * | <-- clkout12
LC24 -> * * * * * * * * * * * * * | - * | <-- clkout10

Pin
43   -> - - - - - - - - - - - - - | - - | <-- clk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\jia\fenpinqi.rpt
fenpinqi

** EQUATIONS **

clk      : INPUT;

-- Node name is 'clkout2' = 'clkout13' 
-- Equation name is 'clkout2', location is LC017, type is output.
clkout2  = clkout13~NOT;
clkout13~NOT = DFFE(!_LC019 $  _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !clkout2 & !clkout4 &  clkout10 &  clkout12 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  _LC019;

-- Node name is 'clkout4' = 'clkout11' 
-- Equation name is 'clkout4', location is LC018, type is output.
clkout4  = clkout11~NOT;
clkout11~NOT = TFFE( clkout10, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':11' = 'clkout10' 
-- Equation name is 'clkout10', location is LC024, type is buried.
clkout10 = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':9' = 'clkout12' 
-- Equation name is 'clkout12', location is LC025, type is buried.
clkout12 = TFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !clkout4 &  clkout10;

-- Node name is ':7' = 'clkout14' 
-- Equation name is 'clkout14', location is LC026, type is buried.
clkout14 = DFFE( _EQ003 $  _LC020, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !clkout2 & !clkout4 &  clkout10 &  clkout12 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  _LC020;

-- Node name is ':6' = 'clkout15' 
-- Equation name is 'clkout15', location is LC027, type is buried.
clkout15 = DFFE( _EQ004 $  _LC021, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 = !clkout2 & !clkout4 &  clkout10 &  clkout12 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  _LC021;

-- Node name is ':5' = 'clkout16' 
-- Equation name is 'clkout16', location is LC028, type is buried.
clkout16 = DFFE( _EQ005 $  _LC022, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !clkout2 & !clkout4 &  clkout10 &  clkout12 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  _LC022;

-- Node name is ':4' = 'clkout17' 
-- Equation name is 'clkout17', location is LC029, type is buried.
clkout17 = DFFE( _EQ006 $  _LC023, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 = !clkout2 & !clkout4 &  clkout10 &  clkout12 &  clkout14 & 
              clkout15 &  clkout16 &  clkout17 &  _LC023;

-- Node name is '|LPM_ADD_SUB:94|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried 
_LC019   = LCELL(!clkout2 $  _EQ007);
  _EQ007 = !clkout4 &  clkout10 &  clkout12;

-- Node name is '|LPM_ADD_SUB:94|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( clkout14 $  _EQ008);
  _EQ008 = !clkout2 & !clkout4 &  clkout10 &  clkout12;

-- Node name is '|LPM_ADD_SUB:94|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried 
_LC021   = LCELL( clkout15 $  _EQ009);
  _EQ009 = !clkout2 & !clkout4 &  clkout10 &  clkout12 &  clkout14;

-- Node name is '|LPM_ADD_SUB:94|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried 
_LC022   = LCELL( clkout16 $  _EQ010);
  _EQ010 = !clkout2 & !clkout4 &  clkout10 &  clkout12 &  clkout14 & 
              clkout15;

-- Node name is '|LPM_ADD_SUB:94|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( clkout17 $  _EQ011);
  _EQ011 = !clkout2 & !clkout4 &  clkout10 &  clkout12 &  clkout14 & 
              clkout15 &  clkout16;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        e:\jia\fenpinqi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,988K