📄 abc.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\jia\abc.rpt
abc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC17 clk4
| +----------------------------- LC18 do
| | +--------------------------- LC23 |FENPINQI:2|clkout12
| | | +------------------------- LC22 |FENPINQI:2|clkout10
| | | | +----------------------- LC21 |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node3
| | | | | +--------------------- LC20 |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node4
| | | | | | +------------------- LC19 |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node5
| | | | | | | +----------------- LC24 |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node6
| | | | | | | | +--------------- LC25 |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node7
| | | | | | | | | +------------- LC32 |SHIFT:1|clkout17
| | | | | | | | | | +----------- LC31 |SHIFT:1|clkout15
| | | | | | | | | | | +--------- LC30 |SHIFT:1|clkout14
| | | | | | | | | | | | +------- LC29 |SHIFT:1|clkout13
| | | | | | | | | | | | | +----- LC28 |SHIFT:1|clkout12
| | | | | | | | | | | | | | +--- LC27 |SHIFT:1|clkout11
| | | | | | | | | | | | | | | +- LC26 |SHIFT:1|clkout10
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> * - * - - - - - - - - - - - - - | - * | <-- clk4
LC18 -> - * - - - - - * * * * * * - - - | - * | <-- do
LC23 -> - * * - - - - - - * * * * * * * | - * | <-- |FENPINQI:2|clkout12
LC22 -> * - * * - - - - - - - - - - - - | - * | <-- |FENPINQI:2|clkout10
LC21 -> - - - - - - - - - - - - * - - - | - * | <-- |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node3
LC20 -> - - - - - - - - - - - * - - - - | - * | <-- |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node4
LC19 -> - - - - - - - - - - * - - - - - | - * | <-- |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node5
LC24 -> - * - - - - - - - - - - - - - - | - * | <-- |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node6
LC25 -> - - - - - - - - - * - - - - - - | - * | <-- |SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node7
LC32 -> - * - - - - - - * * * * * - - - | - * | <-- |SHIFT:1|clkout17
LC31 -> - * - - - - * * * * * * * - - - | - * | <-- |SHIFT:1|clkout15
LC30 -> - * - - - * * * * * * * * - - - | - * | <-- |SHIFT:1|clkout14
LC29 -> - * - - * * * * * * * * * - - - | - * | <-- |SHIFT:1|clkout13
LC28 -> - * - - * * * * * * * * * * - - | - * | <-- |SHIFT:1|clkout12
LC27 -> - * - - * * * * * * * * * * * - | - * | <-- |SHIFT:1|clkout11
LC26 -> - * - - * * * * * * * * * * * * | - * | <-- |SHIFT:1|clkout10
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\jia\abc.rpt
abc
** EQUATIONS **
clk : INPUT;
-- Node name is 'clk4' = '|FENPINQI:2|clkout11'
-- Equation name is 'clk4', type is output
clk4 = _LC017~NOT;
_LC017~NOT = TFFE( _LC022, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'do' = '|SHIFT:1|clkout16'
-- Equation name is 'do', type is output
do = _LC018~NOT;
_LC018~NOT = DFFE(!_LC024 $ _EQ001, !_LC023, VCC, VCC, VCC);
_EQ001 = !do & _LC024 & _LC026 & _LC027 & _LC028 & _LC029 & _LC030 &
_LC031 & _LC032;
-- Node name is '|FENPINQI:2|:6' = '|FENPINQI:2|clkout10'
-- Equation name is '_LC022', type is buried
_LC022 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|FENPINQI:2|:4' = '|FENPINQI:2|clkout12'
-- Equation name is '_LC023', type is buried
_LC023 = TFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !clk4 & _LC022;
-- Node name is '|SHIFT:1|:10' = '|SHIFT:1|clkout10'
-- Equation name is '_LC026', type is buried
_LC026 = TFFE( VCC, !_LC023, VCC, VCC, VCC);
-- Node name is '|SHIFT:1|:9' = '|SHIFT:1|clkout11'
-- Equation name is '_LC027', type is buried
_LC027 = TFFE( _LC026, !_LC023, VCC, VCC, VCC);
-- Node name is '|SHIFT:1|:8' = '|SHIFT:1|clkout12'
-- Equation name is '_LC028', type is buried
_LC028 = TFFE( _EQ003, !_LC023, VCC, VCC, VCC);
_EQ003 = _LC026 & _LC027;
-- Node name is '|SHIFT:1|:7' = '|SHIFT:1|clkout13'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( _EQ004 $ _LC021, !_LC023, VCC, VCC, VCC);
_EQ004 = !do & _LC021 & _LC026 & _LC027 & _LC028 & _LC029 & _LC030 &
_LC031 & _LC032;
-- Node name is '|SHIFT:1|:6' = '|SHIFT:1|clkout14'
-- Equation name is '_LC030', type is buried
_LC030 = DFFE( _EQ005 $ _LC020, !_LC023, VCC, VCC, VCC);
_EQ005 = !do & _LC020 & _LC026 & _LC027 & _LC028 & _LC029 & _LC030 &
_LC031 & _LC032;
-- Node name is '|SHIFT:1|:5' = '|SHIFT:1|clkout15'
-- Equation name is '_LC031', type is buried
_LC031 = DFFE( _EQ006 $ _LC019, !_LC023, VCC, VCC, VCC);
_EQ006 = !do & _LC019 & _LC026 & _LC027 & _LC028 & _LC029 & _LC030 &
_LC031 & _LC032;
-- Node name is '|SHIFT:1|:3' = '|SHIFT:1|clkout17'
-- Equation name is '_LC032', type is buried
_LC032 = DFFE( _EQ007 $ _LC025, !_LC023, VCC, VCC, VCC);
_EQ007 = !do & _LC025 & _LC026 & _LC027 & _LC028 & _LC029 & _LC030 &
_LC031 & _LC032;
-- Node name is '|SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried
_LC021 = LCELL( _LC029 $ _EQ008);
_EQ008 = _LC026 & _LC027 & _LC028;
-- Node name is '|SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( _LC030 $ _EQ009);
_EQ009 = _LC026 & _LC027 & _LC028 & _LC029;
-- Node name is '|SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried
_LC019 = LCELL( _LC031 $ _EQ010);
_EQ010 = _LC026 & _LC027 & _LC028 & _LC029 & _LC030;
-- Node name is '|SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried
_LC024 = LCELL(!do $ _EQ011);
_EQ011 = _LC026 & _LC027 & _LC028 & _LC029 & _LC030 & _LC031;
-- Node name is '|SHIFT:1|LPM_ADD_SUB:93|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( _LC032 $ _EQ012);
_EQ012 = !do & _LC026 & _LC027 & _LC028 & _LC029 & _LC030 & _LC031;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\jia\abc.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,419K
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