fenpinqi.vhd

2FSK调制功能

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpinqi is
   port(
clk:in std_logic;
clkout4,clkout2:out std_logic
);
end fenpinqi;
architecture a of fenpinqi is
signal clkout1:std_logic_vector(2 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1') then
   if clkout1="111" then
       clkout1<="000";
   else
       clkout1<=clkout1+1;
   end if;
end if;
end process;
clkout4<= not clkout1(1);
clkout2<= not clkout1(2);
end a;