prev_cmp_dq01.qmsg

有关毕业设计交通灯的ＶＨＤＬ设计

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74160:inst7\|9 data_in GND " "Warning: Reduced register \"74160:inst7\|9\" with stuck data_in port to stuck value GND" {  } { { "74160.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74160:inst7\|8 data_in GND " "Warning: Reduced register \"74160:inst7\|8\" with stuck data_in port to stuck value GND" {  } { { "74160.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_CREATED_ALOAD_CCT" "" "Warning: Converted presettable and clearable register to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." { { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst21\|49 74190:inst21\|49~_emulated 74190:inst21\|49~35 " "Warning: Register \"74190:inst21\|49\" converted into equivalent circuit using register \"74190:inst21\|49~_emulated\" and latch \"74190:inst21\|49~35\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst21\|50 74190:inst21\|50~_emulated 74190:inst21\|50~37 " "Warning: Register \"74190:inst21\|50\" converted into equivalent circuit using register \"74190:inst21\|50~_emulated\" and latch \"74190:inst21\|50~37\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst21\|48 74190:inst21\|48~_emulated 74190:inst21\|48~8 " "Warning: Register \"74190:inst21\|48\" converted into equivalent circuit using register \"74190:inst21\|48~_emulated\" and latch \"74190:inst21\|48~8\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst24\|48 74190:inst24\|48~_emulated 74190:inst24\|48~8 " "Warning: Register \"74190:inst24\|48\" converted into equivalent circuit using register \"74190:inst24\|48~_emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst24\|50 74190:inst24\|50~_emulated 74190:inst24\|48~8 " "Warning: Register \"74190:inst24\|50\" converted into equivalent circuit using register \"74190:inst24\|50~_emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst33\|49 74190:inst33\|49~_emulated 74190:inst24\|48~8 " "Warning: Register \"74190:inst33\|49\" converted into equivalent circuit using register \"74190:inst33\|49~_emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst33\|50 74190:inst33\|50~_emulated 74190:inst24\|48~8 " "Warning: Register \"74190:inst33\|50\" converted into equivalent circuit using register \"74190:inst33\|50~_emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst33\|48 74190:inst33\|48~_emulated 74190:inst24\|48~8 " "Warning: Register \"74190:inst33\|48\" converted into equivalent circuit using register \"74190:inst33\|48~_emulated\" and latch \"74190:inst24\|48~8\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst35\|50 74190:inst35\|50~_emulated 74190:inst35\|50~37 " "Warning: Register \"74190:inst35\|50\" converted into equivalent circuit using register \"74190:inst35\|50~_emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst35\|48 74190:inst35\|48~_emulated 74190:inst35\|50~37 " "Warning: Register \"74190:inst35\|48\" converted into equivalent circuit using register \"74190:inst35\|48~_emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst5\|48 74190:inst5\|48~_emulated 74190:inst35\|50~37 " "Warning: Register \"74190:inst5\|48\" converted into equivalent circuit using register \"74190:inst5\|48~_emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst5\|49 74190:inst5\|49~_emulated 74190:inst35\|50~37 " "Warning: Register \"74190:inst5\|49\" converted into equivalent circuit using register \"74190:inst5\|49~_emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst5\|50 74190:inst5\|50~_emulated 74190:inst35\|50~37 " "Warning: Register \"74190:inst5\|50\" converted into equivalent circuit using register \"74190:inst5\|50~_emulated\" and latch \"74190:inst35\|50~37\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst6\|48 74190:inst6\|48~_emulated 74190:inst6\|48~8 " "Warning: Register \"74190:inst6\|48\" converted into equivalent circuit using register \"74190:inst6\|48~_emulated\" and latch \"74190:inst6\|48~8\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst6\|50 74190:inst6\|50~_emulated 74190:inst6\|48~8 " "Warning: Register \"74190:inst6\|50\" converted into equivalent circuit using register \"74190:inst6\|50~_emulated\" and latch \"74190:inst6\|48~8\"" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Register \"%1!s!\" converted into equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0}  } {  } 0 0 "Converted presettable and clearable register to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 6 " "Info: 6 registers lost all their fanouts during netlist optimizations. The first 6 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst27/7 " "Info: Register \"inst27/7\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst27/8 " "Info: Register \"inst27/8\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst27/9 " "Info: Register \"inst27/9\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst27/26 " "Info: Register \"inst27/26\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst27/41 " "Info: Register \"inst27/41\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst27/65 " "Info: Register \"inst27/65\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "207 " "Info: Implemented 207 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "34 " "Info: Implemented 34 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "170 " "Info: Implemented 170 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 19 14:54:01 2008 " "Info: Processing ended: Sun Oct 19 14:54:01 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 19 14:54:05 2008 " "Info: Processing started: Sun Oct 19 14:54:05 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off dq01 -c dq01 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dq01 -c dq01" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "dq01 EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"dq01\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}