dq01.fit.qmsg

有关毕业设计交通灯的ＶＨＤＬ设计

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.593 ns register register " "Info: Estimated most critical path is register to register delay of 2.593 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74160:inst7\|7 1 REG LAB_X18_Y16 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X18_Y16; Fanout = 4; REG Node = '74160:inst7\|7'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74160:inst7|7 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.203 ns) + CELL(0.420 ns) 0.623 ns inst25~20 2 COMB LAB_X18_Y16 8 " "Info: 2: + IC(0.203 ns) + CELL(0.420 ns) = 0.623 ns; Loc. = LAB_X18_Y16; Fanout = 8; COMB Node = 'inst25~20'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.623 ns" { 74160:inst7|7 inst25~20 } "NODE_NAME" } } { "dq01.bdf" "" { Schematic "G:/东东/成功红绿灯/dq01.bdf" { { 1344 600 664 1392 "inst25" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 1.188 ns 74190:inst24\|48~98 3 COMB LAB_X18_Y16 10 " "Info: 3: + IC(0.127 ns) + CELL(0.438 ns) = 1.188 ns; Loc. = LAB_X18_Y16; Fanout = 10; COMB Node = '74190:inst24\|48~98'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { inst25~20 74190:inst24|48~98 } "NODE_NAME" } } { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.275 ns) 1.753 ns 74190:inst24\|39~43 4 COMB LAB_X18_Y16 2 " "Info: 4: + IC(0.290 ns) + CELL(0.275 ns) = 1.753 ns; Loc. = LAB_X18_Y16; Fanout = 2; COMB Node = '74190:inst24\|39~43'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { 74190:inst24|48~98 74190:inst24|39~43 } "NODE_NAME" } } { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 984 688 752 1056 "39" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(0.150 ns) 2.509 ns 74190:inst24\|51~152 5 COMB LAB_X17_Y16 1 " "Info: 5: + IC(0.606 ns) + CELL(0.150 ns) = 2.509 ns; Loc. = LAB_X17_Y16; Fanout = 1; COMB Node = '74190:inst24\|51~152'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.756 ns" { 74190:inst24|39~43 74190:inst24|51~152 } "NODE_NAME" } } { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 1048 1008 1072 1128 "51" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.593 ns 74190:inst24\|51 6 REG LAB_X17_Y16 7 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.593 ns; Loc. = LAB_X17_Y16; Fanout = 7; REG Node = '74190:inst24\|51'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { 74190:inst24|51~152 74190:inst24|51 } "NODE_NAME" } } { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 1048 1008 1072 1128 "51" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.367 ns ( 52.72 % ) " "Info: Total cell delay = 1.367 ns ( 52.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.226 ns ( 47.28 % ) " "Info: Total interconnect delay = 1.226 ns ( 47.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.593 ns" { 74160:inst7|7 inst25~20 74190:inst24|48~98 74190:inst24|39~43 74190:inst24|51~152 74190:inst24|51 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}