dq01.tan.qmsg

有关毕业设计交通灯的ＶＨＤＬ设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Spe register 74160:inst7\|6 register 74190:inst24\|48~8 66.12 MHz 15.124 ns Internal " "Info: Clock \"Spe\" has Internal fmax of 66.12 MHz between source register \"74160:inst7\|6\" and destination register \"74190:inst24\|48~8\" (period= 15.124 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.199 ns + Longest register register " "Info: + Longest register to register delay is 1.199 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74160:inst7\|6 1 REG LCFF_X18_Y16_N23 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y16_N23; Fanout = 16; REG Node = '74160:inst7\|6'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74160:inst7|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.521 ns) + CELL(0.242 ns) 0.763 ns inst25~20 2 COMB LCCOMB_X18_Y16_N0 8 " "Info: 2: + IC(0.521 ns) + CELL(0.242 ns) = 0.763 ns; Loc. = LCCOMB_X18_Y16_N0; Fanout = 8; COMB Node = 'inst25~20'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/qu