dq01.tan.qmsg

有关毕业设计交通灯的ＶＨＤＬ设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "inputclock " "Info: Assuming node \"inputclock\" is an undefined clock" {  } { { "dq01.bdf" "" { Schematic "G:/东东/成功红绿灯/dq01.bdf" { { 288 320 488 304 "inputclock" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "inputclock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Reset " "Info: Assuming node \"Reset\" is an undefined clock" {  } { { "dq01.bdf" "" { Schematic "G:/东东/成功红绿灯/dq01.bdf" { { 528 352 520 544 "Reset" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Reset" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Spe " "Info: Assuming node \"Spe\" is an undefined clock" {  } { { "dq01.bdf" "" { Schematic "G:/东东/成功红绿灯/dq01.bdf" { { 344 336 504 360 "Spe" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Spe" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "45 " "Warning: Found 45 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "74190:inst35\|50~37 " "Info: Detected ripple clock \"74190:inst35\|50~37\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst35\|50~37" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst24\|48~8 " "Info: Detected ripple clock \"74190:inst24\|48~8\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst24\|48~8" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst21\|50~37 " "Info: Detected ripple clock \"74190:inst21\|50~37\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst21\|50~37" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst21\|49~35 " "Info: Detected ripple clock \"74190:inst21\|49~35\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst21\|49~35" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst6\|48~8 " "Info: Detected ripple clock \"74190:inst6\|48~8\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|48~8" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst21\|48~8 " "Info: Detected ripple clock \"74190:inst21\|48~8\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst21\|48~8" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst35\|48~_emulated " "Info: Detected ripple clock \"74190:inst35\|48~_emulated\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst35\|48~_emulated" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst35\|48~136 " "Info: Detected gated clock \"74190:inst35\|48~136\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst35\|48~136" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst35\|49 " "Info: Detected ripple clock \"74190:inst35\|49\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst35\|49" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst35\|50~_emulated " "Info: Detected ripple clock \"74190:inst35\|50~_emulated\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst35\|50~_emulated" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst35\|39~47 " "Info: Detected gated clock \"74190:inst35\|39~47\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 984 688 752 1056 "39" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst35\|39~47" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst35\|50~234 " "Info: Detected gated clock \"74190:inst35\|50~234\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst35\|50~234" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst35\|51 " "Info: Detected ripple clock \"74190:inst35\|51\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 1048 1008 1072 1128 "51" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst35\|51" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst35\|58 " "Info: Detected gated clock \"74190:inst35\|58\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 80 1016 1080 120 "58" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst35\|58" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst24\|50~_emulated " "Info: Detected ripple clock \"74190:inst24\|50~_emulated\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst24\|50~_emulated" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst24\|50~187 " "Info: Detected gated clock \"74190:inst24\|50~187\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst24\|50~187" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst24\|49 " "Info: Detected ripple clock \"74190:inst24\|49\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst24\|49" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst24\|51 " "Info: Detected ripple clock \"74190:inst24\|51\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 1048 1008 1072 1128 "51" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst24\|51" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst24\|48~_emulated " "Info: Detected ripple clock \"74190:inst24\|48~_emulated\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst24\|48~_emulated" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "7447:inst26\|38~61 " "Info: Detected gated clock \"7447:inst26\|38~61\" as buffer" {  } { { "7447.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/7447.bdf" { { 1032 592 656 1104 "38" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "7447:inst26\|38~61" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst24\|48~98 " "Info: Detected gated clock \"74190:inst24\|48~98\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst24\|48~98" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst24\|58 " "Info: Detected gated clock \"74190:inst24\|58\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 80 1016 1080 120 "58" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst24\|58" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74160:inst7\|7 " "Info: Detected ripple clock \"74160:inst7\|7\" as buffer" {  } { { "74160.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74160:inst7\|7" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst6\|39~47 " "Info: Detected gated clock \"74190:inst6\|39~47\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 984 688 752 1056 "39" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|39~47" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst6\|50~_emulated " "Info: Detected ripple clock \"74190:inst6\|50~_emulated\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|50~_emulated" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "inst25~20 " "Info: Detected gated clock \"inst25~20\" as buffer" {  } { { "dq01.bdf" "" { Schematic "G:/东东/成功红绿灯/dq01.bdf" { { 1344 600 664 1392 "inst25" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "inst25~20" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst5\|50~_emulated " "Info: Detected ripple clock \"74190:inst5\|50~_emulated\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst5\|50~_emulated" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "inst25~21 " "Info: Detected gated clock \"inst25~21\" as buffer" {  } { { "dq01.bdf" "" { Schematic "G:/东东/成功红绿灯/dq01.bdf" { { 1344 600 664 1392 "inst25" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "inst25~21" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst5\|49~_emulated " "Info: Detected ripple clock \"74190:inst5\|49~_emulated\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst5\|49~_emulated" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst6\|58 " "Info: Detected gated clock \"74190:inst6\|58\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 80 1016 1080 120 "58" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|58" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst6\|48~_emulated " "Info: Detected ripple clock \"74190:inst6\|48~_emulated\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|48~_emulated" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "7408:inst3\|4 " "Info: Detected gated clock \"7408:inst3\|4\" as buffer" {  } { { "7408.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/7408.bdf" { { 160 296 360 200 "4" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "7408:inst3\|4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst5\|48~_emulated " "Info: Detected ripple clock \"74190:inst5\|48~_emulated\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst5\|48~_emulated" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst6\|49 " "Info: Detected ripple clock \"74190:inst6\|49\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|49" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst6\|50~167 " "Info: Detected gated clock \"74190:inst6\|50~167\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|50~167" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst6\|51 " "Info: Detected ripple clock \"74190:inst6\|51\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 1048 1008 1072 1128 "51" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|51" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst5\|50~187 " "Info: Detected gated clock \"74190:inst5\|50~187\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst5\|50~187" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst5\|49~193 " "Info: Detected gated clock \"74190:inst5\|49~193\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst5\|49~193" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74190:inst5\|51 " "Info: Detected ripple clock \"74190:inst5\|51\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 1048 1008 1072 1128 "51" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst5\|51" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst6\|48~76 " "Info: Detected gated clock \"74190:inst6\|48~76\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|48~76" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst5\|48~70 " "Info: Detected gated clock \"74190:inst5\|48~70\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst5\|48~70" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst6\|57~52 " "Info: Detected gated clock \"74190:inst6\|57~52\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 664 688 752 704 "57" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst6\|57~52" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "74190:inst5\|57~53 " "Info: Detected gated clock \"74190:inst5\|57~53\" as buffer" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 664 688 752 704 "57" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74190:inst5\|57~53" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74292:inst27\|126 " "Info: Detected ripple clock \"74292:inst27\|126\" as buffer" {  } { { "74292.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74292.bdf" { { 3368 1192 1256 3448 "126" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74292:inst27\|126" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "74160:inst7\|6 " "Info: Detected ripple clock \"74160:inst7\|6\" as buffer" {  } { { "74160.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "74160:inst7\|6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}