dq01.tan.qmsg

有关毕业设计交通灯的ＶＨＤＬ设计

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off dq01 -c dq01 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dq01 -c dq01 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "74190:inst21\|48~8 " "Warning: Node \"74190:inst21\|48~8\" is a latch" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "74190:inst6\|48~8 " "Warning: Node \"74190:inst6\|48~8\" is a latch" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "74190:inst21\|49~35 " "Warning: Node \"74190:inst21\|49~35\" is a latch" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "74190:inst21\|50~37 " "Warning: Node \"74190:inst21\|50~37\" is a latch" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "74190:inst24\|48~8 " "Warning: Node \"74190:inst24\|48~8\" is a latch" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "74190:inst35\|50~37 " "Warning: Node \"74190:inst35\|50~37\" is a latch" {  } { { "74190.bdf" "" { Schematic "d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}