prev_cmp_dq01.map.qmsg

有关毕业设计交通灯的ＶＨＤＬ设计

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74190 74190:inst6 " "Info: Elaborating entity \"74190\" for hierarchy \"74190:inst6\"" {  } { { "dq01.bdf" "inst6" { Schematic "H:/东东/成功红绿灯/dq01.bdf" { { 784 816 936 944 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74190:inst6 " "Info: Elaborated megafunction instantiation \"74190:inst6\"" {  } { { "dq01.bdf" "" { Schematic "H:/东东/成功红绿灯/dq01.bdf" { { 784 816 936 944 "inst6" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7402 7402:inst30 " "Info: Elaborating entity \"7402\" for hierarchy \"7402:inst30\"" {  } { { "dq01.bdf" "inst30" { Schematic "H:/东东/成功红绿灯/dq01.bdf" { { 624 704 768 664 "inst30" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "7402:inst30 " "Info: Elaborated megafunction instantiation \"7402:inst30\"" {  } { { "dq01.bdf" "" { Schematic "H:/东东/成功红绿灯/dq01.bdf" { { 624 704 768 664 "inst30" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7447 7447:inst " "Info: Elaborating entity \"7447\" for hierarchy \"7447:inst\"" {  } { { "dq01.bdf" "inst" { Schematic "H:/东东/成功红绿灯/dq01.bdf" { { 592 1056 1176 752 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "7447:inst " "Info: Elaborated megafunction instantiation \"7447:inst\"" {  } { { "dq01.bdf" "" { Schematic "H:/东东/成功红绿灯/dq01.bdf" { { 592 1056 1176 752 "inst" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "22 " "Info: Ignored 22 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "22 " "Info: Ignored 22 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0 "" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74160:inst7\|9 data_in GND " "Warning (14130): Reduced register \"74160:inst7\|9\" with stuck data_in port to stuck value GND" {  } { { "74160.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74160:inst7\|8 data_in GND " "Warning (14130): Reduced register \"74160:inst7\|8\" with stuck data_in port to stuck value GND" {  } { { "74160.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_CREATED_ALOAD_CCT" "" "Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." { { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst21\|49 74190:inst21\|49~_emulated 74190:inst21\|49~latch " "Warning (13310): Register \"74190:inst21\|49\" is converted into an equivalent circuit using register \"74190:inst21\|49~_emulated\" and latch \"74190:inst21\|49~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst21\|50 74190:inst21\|50~_emulated 74190:inst21\|50~latch " "Warning (13310): Register \"74190:inst21\|50\" is converted into an equivalent circuit using register \"74190:inst21\|50~_emulated\" and latch \"74190:inst21\|50~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst21\|48 74190:inst21\|48~_emulated 74190:inst21\|48~latch " "Warning (13310): Register \"74190:inst21\|48\" is converted into an equivalent circuit using register \"74190:inst21\|48~_emulated\" and latch \"74190:inst21\|48~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst24\|48 74190:inst24\|48~_emulated 74190:inst24\|48~latch " "Warning (13310): Register \"74190:inst24\|48\" is converted into an equivalent circuit using register \"74190:inst24\|48~_emulated\" and latch \"74190:inst24\|48~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst24\|50 74190:inst24\|50~_emulated 74190:inst24\|48~latch " "Warning (13310): Register \"74190:inst24\|50\" is converted into an equivalent circuit using register \"74190:inst24\|50~_emulated\" and latch \"74190:inst24\|48~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst33\|49 74190:inst33\|49~_emulated 74190:inst21\|49~latch " "Warning (13310): Register \"74190:inst33\|49\" is converted into an equivalent circuit using register \"74190:inst33\|49~_emulated\" and latch \"74190:inst21\|49~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst33\|50 74190:inst33\|50~_emulated 74190:inst21\|50~latch " "Warning (13310): Register \"74190:inst33\|50\" is converted into an equivalent circuit using register \"74190:inst33\|50~_emulated\" and latch \"74190:inst21\|50~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst33\|48 74190:inst33\|48~_emulated 74190:inst21\|48~latch " "Warning (13310): Register \"74190:inst33\|48\" is converted into an equivalent circuit using register \"74190:inst33\|48~_emulated\" and latch \"74190:inst21\|48~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst35\|50 74190:inst35\|50~_emulated 74190:inst35\|50~latch " "Warning (13310): Register \"74190:inst35\|50\" is converted into an equivalent circuit using register \"74190:inst35\|50~_emulated\" and latch \"74190:inst35\|50~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst35\|48 74190:inst35\|48~_emulated 74190:inst35\|50~latch " "Warning (13310): Register \"74190:inst35\|48\" is converted into an equivalent circuit using register \"74190:inst35\|48~_emulated\" and latch \"74190:inst35\|50~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst5\|48 74190:inst5\|48~_emulated 74190:inst21\|48~latch " "Warning (13310): Register \"74190:inst5\|48\" is converted into an equivalent circuit using register \"74190:inst5\|48~_emulated\" and latch \"74190:inst21\|48~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst5\|49 74190:inst5\|49~_emulated 74190:inst21\|49~latch " "Warning (13310): Register \"74190:inst5\|49\" is converted into an equivalent circuit using register \"74190:inst5\|49~_emulated\" and latch \"74190:inst21\|49~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 568 1008 1072 648 "49" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst5\|50 74190:inst5\|50~_emulated 74190:inst21\|50~latch " "Warning (13310): Register \"74190:inst5\|50\" is converted into an equivalent circuit using register \"74190:inst5\|50~_emulated\" and latch \"74190:inst21\|50~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst6\|48 74190:inst6\|48~_emulated 74190:inst6\|48~latch " "Warning (13310): Register \"74190:inst6\|48\" is converted into an equivalent circuit using register \"74190:inst6\|48~_emulated\" and latch \"74190:inst6\|48~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 328 1008 1072 408 "48" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "74190:inst6\|50 74190:inst6\|50~_emulated 74190:inst6\|48~latch " "Warning (13310): Register \"74190:inst6\|50\" is converted into an equivalent circuit using register \"74190:inst6\|50~_emulated\" and latch \"74190:inst6\|48~latch\"" {  } { { "74190.bdf" "" { Schematic "e:/quartus/libraries/others/maxplus2/74190.bdf" { { 808 1008 1072 888 "50" "" } } } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 6 " "Info: 6 registers lost all their fanouts during netlist optimizations. The first 6 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "74292:inst27\|7 " "Info: Register \"74292:inst27\|7\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "74292:inst27\|8 " "Info: Register \"74292:inst27\|8\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "74292:inst27\|9 " "Info: Register \"74292:inst27\|9\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "74292:inst27\|26 " "Info: Register \"74292:inst27\|26\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "74292:inst27\|41 " "Info: Register \"74292:inst27\|41\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "74292:inst27\|65 " "Info: Register \"74292:inst27\|65\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "211 " "Info: Implemented 211 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "34 " "Info: Implemented 34 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "174 " "Info: Implemented 174 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Peak virtual memory: 161 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 18 11:04:11 2008 " "Info: Processing ended: Sat Oct 18 11:04:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}