dq01.fit.rpt

有关毕业设计交通灯的ＶＨＤＬ设计

; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in G:/东东/成功红绿灯/dq01.pin.


+----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                        ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Total logic elements                        ; 168 / 33,216 ( < 1 % ) ;
;     -- Combinational with no register       ; 115                    ;
;     -- Register only                        ; 0                      ;
;     -- Combinational with a register        ; 53                     ;
;                                             ;                        ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 94                     ;
;     -- 3 input functions                    ; 50                     ;
;     -- <=2 input functions                  ; 24                     ;
;     -- Register only                        ; 0                      ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 168                    ;
;     -- arithmetic mode                      ; 0                      ;
;                                             ;                        ;
; Total registers*                            ; 53 / 34,593 ( < 1 % )  ;
;     -- Dedicated logic registers            ; 53 / 33,216 ( < 1 % )  ;
;     -- I/O registers                        ; 0 / 1,377 ( 0 % )      ;
;                                             ;                        ;
; Total LABs:  partially or completely used   ; 13 / 2,076 ( < 1 % )   ;
; User inserted logic elements                ; 0                      ;
; Virtual pins                                ; 0                      ;
; I/O pins                                    ; 37 / 475 ( 8 % )       ;
;     -- Clock pins                           ; 3 / 8 ( 38 % )         ;
; Global signals                              ; 5                      ;
; M4Ks                                        ; 0 / 105 ( 0 % )        ;
; Total memory bits                           ; 0 / 483,840 ( 0 % )    ;
; Total RAM block bits                        ; 0 / 483,840 ( 0 % )    ;
; Embedded Multiplier 9-bit elements          ; 0 / 70 ( 0 % )         ;
; PLLs                                        ; 0 / 4 ( 0 % )          ;
; Global clocks                               ; 5 / 16 ( 31 % )        ;
; Average interconnect usage                  ; 0%                     ;
; Peak interconnect usage                     ; 3%                     ;
; Maximum fan-out node                        ; Spe                    ;
; Maximum fan-out                             ; 46                     ;
; Highest non-global fan-out signal           ; Spe                    ;
; Highest non-global fan-out                  ; 46                     ;
; Total fan-out                               ; 747                    ;
; Average fan-out                             ; 2.81                   ;
+---------------------------------------------+------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LogicLock Region Resource Usage                                                                                                                                                                                                              ;
+------------------+--------+-------+--------+-------------+---------------------------+---------------+-------------+-------+--------------+---------+-----------+-------+--------------+--------------+-------------------+------------------+
; LogicLock Region ; Origin ; Width ; Height ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks  ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins  ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ;
+------------------+--------+-------+--------+-------------+---------------------------+---------------+-------------+-------+--------------+---------+-----------+-------+--------------+--------------+-------------------+------------------+
; Root Region      ; X0_Y0  ; 66    ; 37     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0 (0)       ; 0 (0) ; 0 (0)        ; 0 (0)   ; 0 (0)     ; 0 (0) ; 0 (0)        ; 0 (0)        ; 0 (0)             ; 0 (0)            ;
+------------------+--------+-------+--------+-------------+---------------------------+---------------+-------------+-------+--------------+---------+-----------+-------+--------------+--------------+-------------------+------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                       ;