📄 dq01.map.rpt
字号:
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 168 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 53 ;
; -- Dedicated logic registers ; 53 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 37 ;
; Maximum fan-out node ; 7408:inst3|4 ;
; Maximum fan-out ; 51 ;
; Total fan-out ; 742 ;
; Average fan-out ; 2.88 ;
+---------------------------------------------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |dq01 ; 168 (9) ; 53 (0) ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; |dq01 ; work ;
; |7408:inst1| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|7408:inst1 ; work ;
; |7408:inst3| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|7408:inst3 ; work ;
; |74160:inst7| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|74160:inst7 ; work ;
; |74175:inst45| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|74175:inst45 ; work ;
; |74190:inst21| ; 12 (12) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|74190:inst21 ; work ;
; |74190:inst24| ; 9 (9) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|74190:inst24 ; work ;
; |74190:inst33| ; 9 (9) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|74190:inst33 ; work ;
; |74190:inst35| ; 9 (9) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|74190:inst35 ; work ;
; |74190:inst5| ; 10 (10) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|74190:inst5 ; work ;
; |74190:inst6| ; 10 (10) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|74190:inst6 ; work ;
; |74292:inst27| ; 33 (33) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|74292:inst27 ; work ;
; |7447:inst26| ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|7447:inst26 ; work ;
; |7447:inst39| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|7447:inst39 ; work ;
; |7447:inst40| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|7447:inst40 ; work ;
; |7447:inst| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dq01|7447:inst ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; inst27/7 ; Lost fanout ;
; inst27/8 ; Lost fanout ;
; inst27/9 ; Lost fanout ;
; inst27/26 ; Lost fanout ;
; inst27/41 ; Lost fanout ;
; inst27/65 ; Lost fanout ;
; inst7/9 ; Stuck at GND due to stuck port data_in ;
; inst7/8 ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 8 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 53 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 24 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 6 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Sun Oct 19 14:53:52 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dq01 -c dq01
Info: Found 1 design units, including 1 entities, in source file dq01.bdf
Info: Found entity 1: dq01
Info: Elaborating entity "dq01" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file d:/altera/71/quartus/libraries/others/maxplus2/7404.bdf
Info: Found entity 1: 7404
Info: Elaborating entity "7404" for hierarchy "7404:inst22"
Info: Elaborated megafunction instantiation "7404:inst22"
Info: Found 1 design units, including 1 entities, in source file d:/altera/71/quartus/libraries/others/maxplus2/74175.bdf
Info: Found entity 1: 74175
Info: Elaborating entity "74175" for hierarchy "74175:inst45"
Info: Elaborated megafunction instantiation "74175:inst45"
Info: Found 1 design units, including 1 entities, in source file d:/altera/71/quartus/libraries/others/maxplus2/74292.bdf
Info: Found entity 1: 74292
Info: Elaborating entity "74292" for hierarchy "74292:inst27"
Info: Elaborated megafunction instantiation "74292:inst27"
Info: Found 1 design units, including 1 entities, in source file d:/altera/71/quartus/libraries/others/maxplus2/74160.bdf
Info: Found entity 1: 74160
Info: Elaborating entity "74160" for hierarchy "74160:inst7"
Info: Elaborated megafunction instantiation "74160:inst7"
Info: Found 1 design units, including 1 entities, in source file d:/altera/71/quartus/libraries/others/maxplus2/7408.bdf
Info: Found entity 1: 7408
Info: Elaborating entity "7408" for hierarchy "7408:inst1"
Info: Elaborated megafunction instantiation "7408:inst1"
Info: Found 1 design units, including 1 entities, in source file d:/altera/71/quartus/libraries/others/maxplus2/74190.bdf
Info: Found entity 1: 74190
Info: Elaborating entity "74190" for hierarchy "74190:inst6"
Info: Elaborated megafunction instantiation "74190:inst6"
Info: Found 1 design units, including 1 entities, in source file d:/altera/71/quartus/libraries/others/maxplus2/7402.bdf
Info: Found entity 1: 7402
Info: Elaborating entity "7402" for hierarchy "7402:inst30"
Info: Elaborated megafunction instantiation "7402:inst30"
Info: Found 1 design units, including 1 entities, in source file d:/altera/71/quartus/libraries/others/maxplus2/7447.bdf
Info: Found entity 1: 7447
Info: Elaborating entity "7447" for hierarchy "7447:inst"
Info: Elaborated megafunction instantiation "7447:inst"
Info: Ignored 22 buffer(s)
Info: Ignored 22 SOFT buffer(s)
Warning: Reduced register "74160:inst7|9" with stuck data_in port to stuck value GND
Warning: Reduced register "74160:inst7|8" with stuck data_in port to stuck value GND
Warning: Converted presettable and clearable register to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
Warning: Register "74190:inst21|49" converted into equivalent circuit using register "74190:inst21|49~_emulated" and latch "74190:inst21|49~35"
Warning: Register "74190:inst21|50" converted into equivalent circuit using register "74190:inst21|50~_emulated" and latch "74190:inst21|50~37"
Warning: Register "74190:inst21|48" converted into equivalent circuit using register "74190:inst21|48~_emulated" and latch "74190:inst21|48~8"
Warning: Register "74190:inst24|48" converted into equivalent circuit using register "74190:inst24|48~_emulated" and latch "74190:inst24|48~8"
Warning: Register "74190:inst24|50" converted into equivalent circuit using register "74190:inst24|50~_emulated" and latch "74190:inst24|48~8"
Warning: Register "74190:inst33|49" converted into equivalent circuit using register "74190:inst33|49~_emulated" and latch "74190:inst24|48~8"
Warning: Register "74190:inst33|50" converted into equivalent circuit using register "74190:inst33|50~_emulated" and latch "74190:inst24|48~8"
Warning: Register "74190:inst33|48" converted into equivalent circuit using register "74190:inst33|48~_emulated" and latch "74190:inst24|48~8"
Warning: Register "74190:inst35|50" converted into equivalent circuit using register "74190:inst35|50~_emulated" and latch "74190:inst35|50~37"
Warning: Register "74190:inst35|48" converted into equivalent circuit using register "74190:inst35|48~_emulated" and latch "74190:inst35|50~37"
Warning: Register "74190:inst5|48" converted into equivalent circuit using register "74190:inst5|48~_emulated" and latch "74190:inst35|50~37"
Warning: Register "74190:inst5|49" converted into equivalent circuit using register "74190:inst5|49~_emulated" and latch "74190:inst35|50~37"
Warning: Register "74190:inst5|50" converted into equivalent circuit using register "74190:inst5|50~_emulated" and latch "74190:inst35|50~37"
Warning: Register "74190:inst6|48" converted into equivalent circuit using register "74190:inst6|48~_emulated" and latch "74190:inst6|48~8"
Warning: Register "74190:inst6|50" converted into equivalent circuit using register "74190:inst6|50~_emulated" and latch "74190:inst6|48~8"
Info: 6 registers lost all their fanouts during netlist optimizations. The first 6 are displayed below.
Info: Register "inst27/7" lost all its fanouts during netlist optimizations.
Info: Register "inst27/8" lost all its fanouts during netlist optimizations.
Info: Register "inst27/9" lost all its fanouts during netlist optimizations.
Info: Register "inst27/26" lost all its fanouts during netlist optimizations.
Info: Register "inst27/41" lost all its fanouts during netlist optimizations.
Info: Register "inst27/65" lost all its fanouts during netlist optimizations.
Info: Implemented 207 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 34 output pins
Info: Implemented 170 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
Info: Allocated 140 megabytes of memory during processing
Info: Processing ended: Sun Oct 19 14:54:01 2008
Info: Elapsed time: 00:00:09
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -