seg7dec.sim.rpt

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

; Total coverage as a percentage                      ;      60.26 % ;
; Total nodes checked                                 ; 307          ;
; Total output ports checked                          ; 307          ;
; Total output ports with complete 1/0-value coverage ; 185          ;
; Total output ports with no 1/0-value coverage       ; 122          ;
; Total output ports with no 1-value coverage         ; 122          ;
; Total output ports with no 0-value coverage         ; 122          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                  ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; Node Name                                                           ; Output Port Name                                                    ; Output Port Type ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; |seg7dec|bcdin[0]                                                   ; |seg7dec|bcdin[0]                                                   ; out              ;
; |seg7dec|bcdin[1]                                                   ; |seg7dec|bcdin[1]                                                   ; out              ;
; |seg7dec|bcdin[2]                                                   ; |seg7dec|bcdin[2]                                                   ; out              ;
; |seg7dec|bcdin[3]                                                   ; |seg7dec|bcdin[3]                                                   ; out              ;
; |seg7dec|segout[0]                                                  ; |seg7dec|segout[0]                                                  ; pin_out          ;
; |seg7dec|segout[1]                                                  ; |seg7dec|segout[1]                                                  ; pin_out          ;
; |seg7dec|segout[2]                                                  ; |seg7dec|segout[2]                                                  ; pin_out          ;
; |seg7dec|segout[3]                                                  ; |seg7dec|segout[3]                                                  ; pin_out          ;
; |seg7dec|segout[5]                                                  ; |seg7dec|segout[5]                                                  ; pin_out          ;
; |seg7dec|segout[6]                                                  ; |seg7dec|segout[6]                                                  ; pin_out          ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~0                    ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~0                    ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~1                    ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~1                    ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n1_mux_dataout~1 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n1_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n1_mux_dataout   ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n1_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n2_mux_dataout~0 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n2_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~2                    ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~2                    ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n2_mux_dataout~1 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n2_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n2_mux_dataout   ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n2_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n3_mux_dataout~0 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n3_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~3                    ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~3                    ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n3_mux_dataout   ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n3_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~4                    ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~4                    ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~5                    ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~5                    ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n1_mux_dataout~1 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n1_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n1_mux_dataout   ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l2_w0_n1_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l3_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l3_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~6                    ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|_~6                    ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l3_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l3_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l3_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l3_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~0                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~0                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~1                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~1                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n1_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n1_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~2                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~2                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~3                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~3                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n3_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n3_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~4                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~4                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~5                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~5                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~6                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~6                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~7                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~7                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~8                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~8                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~9                    ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~9                    ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n1_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n1_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~10                   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~10                   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~11                   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~11                   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~12                   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~12                   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~13                   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~13                   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~14                   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|_~14                   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l4_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l4_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l4_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l4_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~0                    ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~0                    ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~1                    ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~1                    ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n1_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n1_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~2                    ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~2                    ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n2_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n2_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~3                    ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~3                    ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~4                    ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~4                    ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~5                    ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~5                    ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~6                    ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|_~6                    ; out0             ;