seg7dec.sim.rpt

来自「EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.」· RPT 代码 · 共 477 行 · 第 1/5 页

; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|_~11                   ; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|_~11                   ; out0             ;
; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l3_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l3_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|_~12                   ; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|_~12                   ; out0             ;
; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l3_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l3_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l3_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l3_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|_~13                   ; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|_~13                   ; out0             ;
; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|_~14                   ; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|_~14                   ; out0             ;
; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l4_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l4_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l4_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux0|mux_lpc:auto_generated|l4_w0_n0_mux_dataout   ; out0             ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                     ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; Node Name                                                           ; Output Port Name                                                    ; Output Port Type ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; |seg7dec|segout[4]                                                  ; |seg7dec|segout[4]                                                  ; pin_out          ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n3_mux_dataout~1 ; |seg7dec|lpm_mux:Mux5|mux_5oc:auto_generated|l1_w0_n3_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n2_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n2_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n4_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n4_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n5_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n5_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n6_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n6_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n6_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n6_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n6_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n6_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n7_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n7_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n7_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n7_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n7_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l1_w0_n7_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n1_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n1_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n2_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n2_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n2_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n2_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n2_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n2_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n3_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n3_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n3_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n3_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n3_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l2_w0_n3_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n1_mux_dataout~1 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n1_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n1_mux_dataout   ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l3_w0_n1_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l4_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux4|mux_lpc:auto_generated|l4_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n3_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n3_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n4_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n4_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n5_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n5_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n6_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n6_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n6_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n6_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n6_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n6_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n7_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n7_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n7_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n7_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n7_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l1_w0_n7_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n2_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n2_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n2_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n2_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n2_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n2_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n3_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n3_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n3_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n3_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n3_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l2_w0_n3_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l3_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l3_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l3_w0_n1_mux_dataout~1 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l3_w0_n1_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l3_w0_n1_mux_dataout   ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l3_w0_n1_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l4_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux3|mux_lpc:auto_generated|l4_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n0_mux_dataout~0 ; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n0_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n0_mux_dataout   ; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n0_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n2_mux_dataout~1 ; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n2_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n3_mux_dataout~0 ; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l1_w0_n3_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l2_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux2|mux_5oc:auto_generated|l2_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~1 ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n0_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~0 ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n1_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~0 ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n2_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~1 ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n3_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~0 ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~1 ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n4_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n4_mux_dataout   ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n4_mux_dataout   ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~0 ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~0 ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~1 ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n5_mux_dataout~1 ; out0             ;
; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n5_mux_dataout   ; |seg7dec|lpm_mux:Mux1|mux_lpc:auto_generated|l1_w0_n5_mux_dataout   ; out0             ;