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FIR滤波器的VHDL代码,可以修改冲击函数的值

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
PACKAGE coeffs IS
  TYPE coef_arr IS ARRAY (0 TO 4) OF SIGNED (8 DOWNTO 0);
  CONSTANT coefs:coef_arr:=("111111001","111111011","000001101","000010000","111101101");
END coeffs;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
USE work.coeffs.all;


ENTITY fir IS
PORT(clk,reset:IN STD_LOGIC;
      sample:IN SIGNED(7 DOWNTO 0);
      result:OUT SIGNED(16 DOWNTO 0));
END fir;
ARCHITECTURE beh OF fir IS 
BEGIN 
     main:PROCESS(clk,reset)
     TYPE shift_arr IS ARRAY (4 DOWNTO 0) OF SIGNED(7 DOWNTO 0);
     VARIABLE tmp,old:SIGNED(7 DOWNTO 0);
     VARIABLE pro:SIGNED(16 DOWNTO 0);
     VARIABLE acc:SIGNED(16 DOWNTO 0);
     VARIABLE shift:shift_Arr;
  BEGIN
     IF reset = '1' THEN
        FOR i IN 0 TO 3 LOOP
        shift(i):=(others=>'0');
        END LOOP;
        result<=(others=>'0');
     ELSIF  clk'EVENT AND clk='1' THEN
        tmp:=sample;
        pro:=tmp*coefs(0);
        acc:=pro;
        FOR i IN 3 DOWNTO 0 LOOP
           old:=shift(i);
           pro:=old*coefs(i+1);
           acc:=acc+pro;
           shift(i+1):=shift(1);
        END LOOP;
        shift(0):=tmp;
     result<=acc;
    END IF;
END PROCESS main;
END beh;