mw_c6xxx_csl.c

用离散小波变换实现语音去噪

#include "MW_c6xxx_csl.h"
#include "rtwtypes.h"
#include "dwtdenoising.h"
#include "dwtdenoising_private.h"
#include "dwtdenoisingcfg.h"
#include <hwi.h>
#define _C6XCHIP_SOURCE_FILE_

MCBSP_Handle hMcbsp;

#define NUM_EDMA_BUFFERS               (2)
#define MW_IOM_INPUT                   (0)
#define MW_IOM_OUTPUT                  (1)

typedef struct {
  void *buffer[2];
  EDMA_Handle hEdma;
  EDMA_Handle hEdmaRld[2];
  SEM_Obj sem;
  uint_T dmaBuff;
  uint_T currBuff;
  int_T tcc;
  int_T ioMode;
  uint_T reqCnt;
} EDMA_channel;

#define NUM_EDMA_INPUT_CHANNELS        (1)
#define ADC_EDMA_CHANNEL               (0)
#define NUM_EDMA_OUTPUT_CHANNELS       (1)
#define DAC_EDMA_CHANNEL               (ADC_EDMA_CHANNEL + 1)
#define NUM_EDMA_CHANNELS              (NUM_EDMA_INPUT_CHANNELS + NUM_EDMA_OUTPUT_CHANNELS)

EDMA_channel edmaChan[NUM_EDMA_CHANNELS];

/* Declare DMA buffers used by the DAC driver */
#pragma DATA_ALIGN(txBuff, CACHE_L2_LINESIZE);

#define DAC_BUFF_SIZE                  ( ((FRAME_SIZE * sizeof(int16_T) + CACHE_L2_LINESIZE - 1) & (~(CACHE_L2_LINESIZE - 1))) / sizeof(int16_T) )

volatile int16_T txBuff[ NUM_EDMA_BUFFERS * DAC_BUFF_SIZE ];

/* Declare DMA buffers used by the ADC driver */
#pragma DATA_ALIGN(rxBuff, CACHE_L2_LINESIZE);

#define ADC_BUFF_SIZE                  ( ((FRAME_SIZE * sizeof(int16_T) + CACHE_L2_LINESIZE - 1) & (~(CACHE_L2_LINESIZE - 1))) / sizeof(int16_T) )

volatile int16_T rxBuff[ NUM_EDMA_BUFFERS * ADC_BUFF_SIZE ];
void cslInitialize (void);
void turnOn_L2Cache(void);
void targetInitialize(void)
{
  cslInitialize();
}

void targetTerminate(void)
{
}

TIMER_Handle hTimer1;
void configureTimers(void)
{
  Uint32 timerControl = TIMER_CTL_RMK(
    TIMER_CTL_INVINP_NO,
    TIMER_CTL_CLKSRC_CPUOVR4,
    TIMER_CTL_CP_PULSE,
    TIMER_CTL_HLD_YES,
    TIMER_CTL_GO_NO,
    TIMER_CTL_PWID_ONE,
    TIMER_CTL_DATOUT_0,
    TIMER_CTL_INVOUT_NO,
    TIMER_CTL_FUNC_GPIO
    );
  TIMER_Config timerCfg;
  Uint32 timerEventId;

  // Initialize control and count fields of
  // the timer configuration object
  timerCfg.ctl = timerControl;
  timerCfg.cnt = 0x0;

  // Configure timer for timer interrupt 15
  hTimer1 = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET);
  timerCfg.prd = 7500000U;
  TIMER_config(hTimer1, &timerCfg);
  timerEventId = TIMER_getEventId(hTimer1);
  IRQ_map(timerEventId, 15);
  IRQ_enable(timerEventId);
  TIMER_start(hTimer1);
}

void Timer1_ISR(Uint32 Mailbox)
{
  SEM_post( &rtClockSEM );
}

/* Function: initDMABuffers ----------------------------------
 *
 * Abstract:
 *      Initialize all buffer data to zero
 */
void initDMABuffers(void)
{
  /* Initialize all buffer data to zero */
  memset((void *) &rxBuff[0], 0, NUM_EDMA_BUFFERS * FRAME_SIZE * sizeof(int16_T));
  memset((void *) &txBuff[0], 0, NUM_EDMA_BUFFERS * FRAME_SIZE * sizeof(int16_T));
}

/* Function: initDMAInterrupts -------------------------------
 *
 * Abstract:
 *      This function enables DMA interrupts
 */
void initDMAInterrupts(void)
{
  config_DMA();

  /* Start Rx */
  EDMA_setChannel(edmaChan[ADC_EDMA_CHANNEL].hEdma);

  /* Start Tx */
  EDMA_setChannel(edmaChan[DAC_EDMA_CHANNEL].hEdma);
}

/* Function: disableDMA --------------------------------------
 *
 * Abstract:
 *      This function disables EDMA events
 */
void disable_DMA(void)
{
  EDMA_disableChannel(EDMA_CHA_REVT0);
  EDMA_disableChannel(EDMA_CHA_XEVT0);
}

/* Function: EDMA_isr ----------------------------------------
 *
 * Abstract:
 *      This function is called by the EDMA_intDispatcher and
 *      services interrupts posted by EDMA
 */
void EDMA_isr(int_T tcc)
{
  int_T i;
  for (i = 0; i < NUM_EDMA_CHANNELS; i++) {
    if (edmaChan[i].tcc == tcc) {
      int_T dmaBuff = edmaChan[i].dmaBuff;
      edmaChan[i].currBuff = dmaBuff;  // Save completed DMA buffer pointer
      edmaChan[i].dmaBuff = (dmaBuff + 1) % NUM_EDMA_BUFFERS;// Rotate DMA buffer pointer
      SEM_ipost(&edmaChan[i].sem);
      break;
    }
  }
}

void cslInitialize(void)
{
}

/* Function: enable_interrupts -------------------------------
 *
 * Abstract:
 *      Enable the all DMA and DSP interrupts
 */
void enable_interrupts()
{
  initDMAInterrupts();
}

/* Function: disable_interrupts ------------------------------
 *
 * Abstract:
 *      Disable all DSP interrupts
 */
void disable_interrupts()
{
  IRQ_globalDisable();
}

//
//EOF -- MW_c6xxx_csl.c

/* Function: mcbsp0_write() ----------------------------------
 *
 * Abstract:
 *      This function writes to McBSP 0
 */
void mcbsp0_write (unsigned int out_data)
{
  while (!(MCBSP_xrdy(hMcbsp))) ;
  MCBSP_write( hMcbsp, out_data );
}

/* Function: mcbsp0_read() -----------------------------------
 *
 * Abstract:
 *      This function reads from McBSP 0
 */
unsigned int mcbsp0_read (void)
{
  while (!(MCBSP_rrdy(hMcbsp))) ;
  return (MCBSP_read(hMcbsp));
}

/* Function: config_McBSP ----------------------------------------------
 *
 * Abstract:
 *      This function configures McBSP 0
 */
void config_McBSP(int port)
{
  const int mcbspDev = MCBSP_DEV0;
  hMcbsp = MCBSP_open( mcbspDev, MCBSP_OPEN_RESET );

  /* Configure the Serial Port */
  MCBSP_configArgs(
                   hMcbsp,
                   MCBSP_SPCR_RMK(
    MCBSP_SPCR_FREE_YES,
    MCBSP_SPCR_SOFT_NO,
    MCBSP_SPCR_FRST_YES,
    MCBSP_SPCR_GRST_YES,
    MCBSP_SPCR_XINTM_XRDY,
    MCBSP_SPCR_XSYNCERR_NO,
    MCBSP_SPCR_XRST_NO,
    MCBSP_SPCR_DLB_OFF,
    MCBSP_SPCR_RJUST_RZF,
    MCBSP_SPCR_CLKSTP_DISABLE,
    MCBSP_SPCR_DXENA_OFF,
    MCBSP_SPCR_RINTM_RRDY,
    MCBSP_SPCR_RSYNCERR_NO,
    MCBSP_SPCR_RRST_NO
    ),
                   MCBSP_RCR_RMK(
    MCBSP_RCR_RPHASE_SINGLE,
    MCBSP_RCR_RFRLEN2_OF(0),
    MCBSP_RCR_RWDLEN2_8BIT,            /* Not using Phase */
    MCBSP_RCR_RCOMPAND_MSB,
    MCBSP_RCR_RFIG_YES,
    MCBSP_RCR_RDATDLY_1BIT,
    MCBSP_RCR_RFRLEN1_OF(0),
    MCBSP_RCR_RWDLEN1_16BIT,
    MCBSP_RCR_RWDREVRS_DISABLE
    ),
                   MCBSP_XCR_RMK(
    MCBSP_XCR_XPHASE_SINGLE,
    MCBSP_XCR_XFRLEN2_OF(0),
    MCBSP_XCR_XWDLEN2_8BIT,            /* Not using Phase */
    MCBSP_XCR_XCOMPAND_MSB,
    MCBSP_XCR_XFIG_YES,
    MCBSP_XCR_XDATDLY_1BIT,
    MCBSP_XCR_XFRLEN1_OF(0),
    MCBSP_XCR_XWDLEN1_16BIT,
    MCBSP_XCR_XWDREVRS_DISABLE
    ),
                   MCBSP_SRGR_DEFAULT,
                   MCBSP_MCR_DEFAULT,
                   MCBSP_RCER_DEFAULT,
                   MCBSP_XCER_DEFAULT,
                   MCBSP_PCR_DEFAULT
                   );
}

void config_DMA(void)
{
  const int rcvEvent = EDMA_CHA_REVT0;
  const int xmtEvent = EDMA_CHA_XEVT0;
  const int_T elCnt = FRAME_SIZE;
  uint32_T mcBspRcvAddr = MCBSP_getRcvAddr(hMcbsp);
  uint32_T mcBspXmtAddr = MCBSP_getXmtAddr(hMcbsp);
  EDMA_Config edmaCfg = { EDMA_OPT_RMK(
    EDMA_OPT_PRI_HIGH,
    EDMA_OPT_ESIZE_16BIT,
    EDMA_OPT_2DS_NO,
    EDMA_OPT_SUM_NONE,
    EDMA_OPT_2DD_NO,
    EDMA_OPT_DUM_NONE,
    EDMA_OPT_TCINT_YES,
    EDMA_OPT_TCC_OF(0),
    EDMA_OPT_LINK_YES,
    EDMA_OPT_FS_NO),
    NULL,
    FRAME_SIZE,
    NULL,
    EDMA_IDX_DEFAULT,
    EDMA_RLD_OF(0)
  };

  int_T i;
  HWI_Attrs hwiAttrs;

  // Map DMA controller interrupt to IRQ(8)
  IRQ_map(IRQ_EVT_EDMAINT, 8);

  // Set the interrupt mask for the EDMA interrupt.
  // Disable all interrupts while processing EDMA ISR.
  // We consider all other interrupts, including base rate
  // timer, BIOS system timer, RTDX and user installed interrupts
  // to be of lower priority than the DMA interrupt.
  hwiAttrs.intrMask = IRQ_IEMASK_ALL;  // Mask all interrupts during EDMA ISR
  hwiAttrs.ccMask = IRQ_CCMASK_NONE;   // Do not modify cache control
  hwiAttrs.arg = NULL;

  // Plug the EDMA dispatcher into the HWI(8)
  HWI_dispatchPlug(8, (Fxn) EDMA_intDispatcher, -1, &hwiAttrs);

  // ***************************************************
  // Set parameters of the ADC EDMA channel
  //
  edmaChan[ADC_EDMA_CHANNEL].ioMode = MW_IOM_INPUT;
  edmaChan[ADC_EDMA_CHANNEL].hEdma = EDMA_open( rcvEvent, EDMA_OPEN_RESET );
  edmaChan[ADC_EDMA_CHANNEL].tcc = EDMA_intAlloc(-1);
  edmaChan[ADC_EDMA_CHANNEL].dmaBuff = 0;
  edmaChan[ADC_EDMA_CHANNEL].currBuff = 0;
  EDMA_FSETA(&edmaCfg, OPT, SUM, EDMA_OPT_SUM_NONE);
  EDMA_FSETA(&edmaCfg, OPT, DUM, EDMA_OPT_DUM_INC);
  EDMA_FSETA(&edmaCfg, OPT, TCC, edmaChan[ADC_EDMA_CHANNEL].tcc);
  edmaCfg.src = mcBspRcvAddr;
  edmaCfg.dst = (uint32_T) &rxBuff[0];
  edmaCfg.cnt = EDMA_FMK(CNT, ELECNT, elCnt);
  EDMA_config(edmaChan[ADC_EDMA_CHANNEL].hEdma, &edmaCfg);

  // Initialize EDMA reload handles
  for (i = 0; i < NUM_EDMA_BUFFERS; i++) {
    edmaChan[ADC_EDMA_CHANNEL].hEdmaRld[i] = EDMA_allocTable(-1);
    edmaChan[ADC_EDMA_CHANNEL].buffer[i] = (void *) &rxBuff[i * ADC_BUFF_SIZE];
    edmaCfg.dst = (uint32_T) edmaChan[ADC_EDMA_CHANNEL].buffer[i];
    EDMA_config(edmaChan[ADC_EDMA_CHANNEL].hEdmaRld[i], &edmaCfg);
  }

  // Configure and link EDMA reload handles
  for (i = 0; i < NUM_EDMA_BUFFERS; i++) {
    EDMA_link(edmaChan[ADC_EDMA_CHANNEL].hEdmaRld[i], edmaChan[ADC_EDMA_CHANNEL]
              .hEdmaRld[(i + 1) % NUM_EDMA_BUFFERS]);
  }

  EDMA_link(edmaChan[ADC_EDMA_CHANNEL].hEdma, edmaChan[ADC_EDMA_CHANNEL].
            hEdmaRld[1]);

  // We use DSP/BIOS interrupt dispatcher to process DAC EDMA interrupts
  EDMA_intHook(edmaChan[ADC_EDMA_CHANNEL].tcc, &EDMA_isr);

  // Initialize buffer syncronization semaphore
  SEM_new(&edmaChan[ADC_EDMA_CHANNEL].sem, 0);

  // ***************************************************
  // Set parameters of the DAC EDMA channel
  //
  edmaChan[DAC_EDMA_CHANNEL].ioMode = MW_IOM_OUTPUT;
  edmaChan[DAC_EDMA_CHANNEL].hEdma = EDMA_open( xmtEvent, EDMA_OPEN_RESET );
  edmaChan[DAC_EDMA_CHANNEL].tcc = EDMA_intAlloc(-1);
  edmaChan[DAC_EDMA_CHANNEL].dmaBuff = 0;
  edmaChan[DAC_EDMA_CHANNEL].currBuff = 0;
  EDMA_FSETA(&edmaCfg, OPT, SUM, EDMA_OPT_SUM_INC);
  EDMA_FSETA(&edmaCfg, OPT, DUM, EDMA_OPT_DUM_NONE);
  EDMA_FSETA(&edmaCfg, OPT, TCC, edmaChan[DAC_EDMA_CHANNEL].tcc);
  edmaCfg.src = (uint32_T) &txBuff[0];
  edmaCfg.dst = mcBspXmtAddr;
  edmaCfg.cnt = EDMA_FMK(CNT, ELECNT, elCnt);
  EDMA_config(edmaChan[DAC_EDMA_CHANNEL].hEdma, &edmaCfg);

  // Initialize EDMA reload handles
  for (i = 0; i < NUM_EDMA_BUFFERS; i++) {
    edmaChan[DAC_EDMA_CHANNEL].hEdmaRld[i] = EDMA_allocTable(-1);
    edmaChan[DAC_EDMA_CHANNEL].buffer[i] = (void *) &txBuff[i * DAC_BUFF_SIZE];
    edmaCfg.src = (uint32_T) edmaChan[DAC_EDMA_CHANNEL].buffer[i];
    EDMA_config(edmaChan[DAC_EDMA_CHANNEL].hEdmaRld[i], &edmaCfg);
  }

  // Link EDMA reload entries
  for (i = 0; i < NUM_EDMA_BUFFERS; i++) {
    EDMA_link(edmaChan[DAC_EDMA_CHANNEL].hEdmaRld[i], edmaChan[DAC_EDMA_CHANNEL]
              .hEdmaRld[(i+1) % NUM_EDMA_BUFFERS]);
  }

  EDMA_link(edmaChan[DAC_EDMA_CHANNEL].hEdma, edmaChan[DAC_EDMA_CHANNEL].
            hEdmaRld[1]);

  // We use DSP/BIOS interrupt dispatcher to process DAC EDMA interrupts
  EDMA_intHook(edmaChan[DAC_EDMA_CHANNEL].tcc, &EDMA_isr);

  // Initialize buffer syncronization semaphore
  SEM_new(&edmaChan[DAC_EDMA_CHANNEL].sem, 0);

  // enable EDMA-to-CPU interrupt
  IRQ_enable(IRQ_EVT_EDMAINT);

  // Clear pending interrupts and enable ADC recv channel
  EDMA_intClear( edmaChan[ADC_EDMA_CHANNEL].tcc );
  EDMA_intEnable( edmaChan[ADC_EDMA_CHANNEL].tcc );
  EDMA_enableChannel( edmaChan[ADC_EDMA_CHANNEL].hEdma );

  // Clear pending interrupts and enable DAC transmit channel
  EDMA_intClear( edmaChan[DAC_EDMA_CHANNEL].tcc );
  EDMA_intEnable( edmaChan[DAC_EDMA_CHANNEL].tcc );
  EDMA_enableChannel( edmaChan[DAC_EDMA_CHANNEL].hEdma );
}

void *getDacBuff(void)
{
  int_T currBuff;

  //block until DAC buffer is ready
  SEM_pend(&edmaChan[DAC_EDMA_CHANNEL].sem, SYS_FOREVER);
  currBuff = edmaChan[DAC_EDMA_CHANNEL].currBuff;
  return(edmaChan[DAC_EDMA_CHANNEL].buffer[currBuff]);
}

void *getAdcBuff(void)
{
  int_T currBuff;

  //block until ADC buffer is ready
  SEM_pend(&edmaChan[ADC_EDMA_CHANNEL].sem, SYS_FOREVER);
  currBuff = edmaChan[ADC_EDMA_CHANNEL].currBuff;
  return(edmaChan[ADC_EDMA_CHANNEL].buffer[currBuff]);
}
void turnOn_L2Cache()
{
    CACHE_setL2Mode (CACHE_48KCACHE);
    CACHE_enableCaching (CACHE_CE00);
}