set_s_m_h.vhd

VHDL多功能时钟设计~~24小时制~带闹钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity set_s_m_h is
port(en,add,cout:in std_logic;
              clk:out std_logic);
end;
architecture one of set_s_m_h is
 begin
  process(en,add,cout)
   begin
    if en='0' then 
     clk<=cout;else clk<=add;
    end if;
    end process;
end one;