addm1224.vhd

VHDL多功能时钟设计~~24小时制~带闹钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addm1224 is
port(hms,addin,clk1khz:in std_logic;
     m12_24,addout:out std_logic);
end addm1224;
architecture one of addm1224 is
 begin
  process(hms,addin,clk1khz)
   begin
     if rising_edge(clk1khz) then
      if hms='1' then
      m12_24<=addin;
      else addout<=addin;
      end if;
     end if;
end process;
end one;