choice.vhd

VHDL多功能时钟设计~~24小时制~带闹钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity choice is
port(cho:in std_logic;
     enh,enm,ens:out std_logic);
end ;
architecture one of choice is
signal s:integer range 0 to 3;
 begin
  process(cho)
   begin
    if rising_edge(cho) then
     case s is
      when 0=>s<=1;enh<='1';enm<='0';ens<='0';
      when 1=>s<=2;enm<='1';enh<='0';ens<='0';
      when 2=>s<=3;ens<='1';enh<='0';enm<='0';
      when 3=>s<=0;enh<='0';ens<='0';enm<='0';
      when others=>null;
     end case;
    end if;
end process;
end one;