clkgen.vhd

来自「VHDL多功能时钟设计~~24小时制~带闹钟」· VHDL 代码 · 共 44 行

library ieee;
use ieee.std_logic_1164.all;
entity clkgen is
port (clk: in std_logic;
      clk1hz, clk500hz, clk1khz: out std_logic);
end entity clkgen;
architecture one of clkgen is
  signal cnter1 : integer range 0 to 10#2999999#;
  signal cnter2 : integer range 0 to 10#2999#;
  signal cnter3 : integer range 0 to 10#5999#;
   begin
    process(clk) is
     begin
      if clk'event and clk='1' then
        if cnter1=10#2999999# then cnter1<=0;
        else cnter1<=cnter1+1;
        end if;
        if cnter2=10#2999# then cnter2<=0;
        else cnter2<=cnter2+1;
        end if;
        if cnter3=10#5999# then cnter3<=0;
        else cnter3<=cnter3+1;
        end if;
      end if;
    end process;
    process(cnter1) is
      begin
       if cnter1=10#2999999# then clk1hz<='1';
       else clk1hz<='0';
       end if;
       end process;
    process(cnter2) is
      begin
       if cnter2=10#2999# then clk1khz<='1';
       else clk1khz<='0';
       end if;
       end process;
    process(cnter3) is
      begin
       if cnter3=10#5999# then clk500hz<='1';
       else clk500hz<='0';
       end if;
       end process;
end architecture one;