cnt10.vhd

来自「VHDL多功能时钟设计~~24小时制~带闹钟」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port (clk, clr, ena: in std_logic;
                 cq: out std_logic_vector(3 downto 0);
                 ca: out std_logic);
end entity cnt10;
architecture one of cnt10 is
  begin
  process (clk, clr, ena)
  variable cqi:std_logic_vector(3 downto 0);
    begin
     if clr='1' then cqi:= (others =>'0');
     elsif clk'event and clk='1' then
      if ena='1' then
       if cqi<9 then cqi:=cqi+1;
       else cqi := (others =>'0');
       end if;
      end if;
     end if;
     if cqi=0 then ca<='1';
     else ca<='0';
     end if;
cq<=cqi;
  end process;
end architecture one;