onff.vhd

VHDL多功能时钟设计~~24小时制~带闹钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity onff is
   port(cho, add, bm:in std_logic;
        choclock, addclock, chodate, adddate, enapao, clrpao, chonao, addnao:out std_logic);
end onff;
architecture one of onff is  
signal ms: integer range 0 to 3;
 begin
  process(bm,cho,add,ms)
   begin
    if ms<4 then
     if rising_edge(bm) then ms<=ms+1;
     end if;
    else ms<=0;
    end if;
     case ms is
      when 0=>
      choclock<=cho;
      addclock<=add;
      chodate<='0';
      adddate<='0';
      chonao<='0';
      addnao<='0';
      enapao<='0';
      clrpao<='0';
      when 1=>
      chodate<=cho;
      adddate<=add;
      chonao<='0';
      addnao<='0';
      choclock<='0';
      addclock<='0';
      enapao<='0';
      clrpao<='0';
      when 2=>
      clrpao<=cho;
      enapao<=add;
      chodate<='0';
      adddate<='0';
      choclock<='0';
      addclock<='0';
      chonao<='0';
      addnao<='0'; 
      when 3=>
      chonao<=cho;
      addnao<=add;
      chodate<='0';
      adddate<='0';
      choclock<='0';
      addclock<='0';
      enapao<='0';
      clrpao<='0'; 
      when others=>
      null;
      end case;
end process;
end;