topclock.hier_info

VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.

|topclock
clk => second:u1.clk
reset => alar:u4.reset
reset => hour:u3.reset
reset => minute:u2.reset
reset => second:u1.reset
enable => alar:u4.enable
cles => second:u1.cles
clem => minute:u2.clem
cleh => hour:u3.cleh
setm[0] => alar:u4.setm[0]
setm[1] => alar:u4.setm[1]
setm[2] => alar:u4.setm[2]
setm[3] => alar:u4.setm[3]
setm[4] => alar:u4.setm[4]
setm[5] => alar:u4.setm[5]
seth[0] => alar:u4.seth[0]
seth[1] => alar:u4.seth[1]
seth[2] => alar:u4.seth[2]
seth[3] => alar:u4.seth[3]
seth[4] => alar:u4.seth[4]
alarm <= alar:u4.alarm
baoshi <= baoshi~0.DB_MAX_OUTPUT_PORT_TYPE
seco[0] <= second:u1.sec[0]
seco[1] <= second:u1.sec[1]
seco[2] <= second:u1.sec[2]
seco[3] <= second:u1.sec[3]
seco[4] <= second:u1.sec[4]
seco[5] <= second:u1.sec[5]
minu[0] <= minute:u2.min[0]
minu[1] <= minute:u2.min[1]
minu[2] <= minute:u2.min[2]
minu[3] <= minute:u2.min[3]
minu[4] <= minute:u2.min[4]
minu[5] <= minute:u2.min[5]
houu[0] <= hour:u3.hou[0]
houu[1] <= hour:u3.hou[1]
houu[2] <= hour:u3.hou[2]
houu[3] <= hour:u3.hou[3]
houu[4] <= hour:u3.hou[4]


|topclock|second:u1
reset => counter[5]~0.IN0
reset => carry_out2.ENA
reset => carry_out1.ENA
clk => counter[5].CLK
clk => counter[4].CLK
clk => counter[3].CLK
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => carry_out1.CLK
clk => carry_out2.CLK
setmin => ~NO_FANOUT~
cles => counter[5]~0.IN1
spe <= carry_out2.DB_MAX_OUTPUT_PORT_TYPE
sec[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
sec[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
sec[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
sec[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
sec[4] <= counter[4].DB_MAX_OUTPUT_PORT_TYPE
sec[5] <= counter[5].DB_MAX_OUTPUT_PORT_TYPE
enmin <= carry_out1.DB_MAX_OUTPUT_PORT_TYPE


|topclock|minute:u2
reset => counter[5]~0.IN0
reset => carry_out1.ENA
clkm => counter[5].CLK
clkm => counter[4].CLK
clkm => counter[3].CLK
clkm => counter[2].CLK
clkm => counter[1].CLK
clkm => counter[0].CLK
clkm => carry_out1.CLK
clem => counter[5]~0.IN1
min[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
min[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
min[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
min[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
min[4] <= counter[4].DB_MAX_OUTPUT_PORT_TYPE
min[5] <= counter[5].DB_MAX_OUTPUT_PORT_TYPE
enhou <= carry_out1.DB_MAX_OUTPUT_PORT_TYPE
speak <= carry_out1.DB_MAX_OUTPUT_PORT_TYPE


|topclock|hour:u3
reset => counter[4]~0.IN0
clkh => counter[4].CLK
clkh => counter[3].CLK
clkh => counter[2].CLK
clkh => counter[1].CLK
clkh => counter[0].CLK
cleh => counter[4]~0.IN1
hou[0] <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
hou[1] <= counter[1].DB_MAX_OUTPUT_PORT_TYPE
hou[2] <= counter[2].DB_MAX_OUTPUT_PORT_TYPE
hou[3] <= counter[3].DB_MAX_OUTPUT_PORT_TYPE
hou[4] <= counter[4].DB_MAX_OUTPUT_PORT_TYPE


|topclock|alar:u4
enable => ~NO_FANOUT~
reset => ~NO_FANOUT~
setm[0] => ~NO_FANOUT~
setm[1] => ~NO_FANOUT~
setm[2] => ~NO_FANOUT~
setm[3] => ~NO_FANOUT~
setm[4] => ~NO_FANOUT~
setm[5] => ~NO_FANOUT~
seth[0] => ~NO_FANOUT~
seth[1] => ~NO_FANOUT~
seth[2] => ~NO_FANOUT~
seth[3] => ~NO_FANOUT~
seth[4] => ~NO_FANOUT~
minu1[0] => ~NO_FANOUT~
minu1[1] => ~NO_FANOUT~
minu1[2] => ~NO_FANOUT~
minu1[3] => ~NO_FANOUT~
minu1[4] => ~NO_FANOUT~
minu1[5] => ~NO_FANOUT~
houu1[0] => ~NO_FANOUT~
houu1[1] => ~NO_FANOUT~
houu1[2] => ~NO_FANOUT~
houu1[3] => ~NO_FANOUT~
houu1[4] => ~NO_FANOUT~
alarm <= <GND>