prev_cmp_topclock.fit.qmsg

VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.416 ns register register " "Info: Estimated most critical path is register to register delay of 1.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute:u2\|counter\[1\] 1 REG LAB_X15_Y32 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y32; Fanout = 4; REG Node = 'minute:u2\|counter\[1\]'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { minute:u2|counter[1] } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.417 ns) + CELL(0.322 ns) 0.739 ns minute:u2\|LessThan0~77 2 COMB LAB_X15_Y32 1 " "Info: 2: + IC(0.417 ns) + CELL(0.322 ns) = 0.739 ns; Loc. = LAB_X15_Y32; Fanout = 1; COMB Node = 'minute:u2\|LessThan0~77'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.739 ns" { minute:u2|counter[1] minute:u2|LessThan0~77 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/studys/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.449 ns) 1.320 ns minute:u2\|LessThan0~78 3 COMB LAB_X15_Y32 7 " "Info: 3: + IC(0.132 ns) + CELL(0.449 ns) = 1.320 ns; Loc. = LAB_X15_Y32; Fanout = 7; COMB Node = 'minute:u2\|LessThan0~78'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.581 ns" { minute:u2|LessThan0~77 minute:u2|LessThan0~78 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/studys/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.416 ns minute:u2\|carry_out1 4 REG LAB_X15_Y32 2 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 1.416 ns; Loc. = LAB_X15_Y32; Fanout = 2; REG Node = 'minute:u2\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { minute:u2|LessThan0~78 minute:u2|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.867 ns ( 61.23 % ) " "Info: Total cell delay = 0.867 ns ( 61.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.549 ns ( 38.77 % ) " "Info: Total interconnect delay = 0.549 ns ( 38.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.416 ns" { minute:u2|counter[1] minute:u2|LessThan0~77 minute:u2|LessThan0~78 minute:u2|carry_out1 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y24 X21_Y36 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y24 to location X21_Y36" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}