topclock.tan.qmsg

VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.

{ "Info" "ITDB_TH_RESULT" "minute:u2\|carry_out1 reset clk -2.068 ns register " "Info: th for register \"minute:u2\|carry_out1\" (data pin = \"reset\", clock pin = \"clk\") is -2.068 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.816 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 4.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.735 ns) + CELL(0.879 ns) 3.650 ns second:u1\|carry_out1 2 REG LCFF_X16_Y32_N13 2 " "Info: 2: + IC(1.735 ns) + CELL(0.879 ns) = 3.650 ns; Loc. = LCFF_X16_Y32_N13; Fanout = 2; REG Node = 'second:u1\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { clk second:u1|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.602 ns) 4.816 ns minute:u2\|carry_out1 3 REG LCFF_X15_Y32_N3 2 " "Info: 3: + IC(0.564 ns) + CELL(0.602 ns) = 4.816 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.166 ns" { second:u1|carry_out1 minute:u2|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.517 ns ( 52.26 % ) " "Info: Total cell delay = 2.517 ns ( 52.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.299 ns ( 47.74 % ) " "Info: Total interconnect delay = 2.299 ns ( 47.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.816 ns" { clk second:u1|carry_out1 minute:u2|carry_out1 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "4.816 ns" { clk {} clk~combout {} second:u1|carry_out1 {} minute:u2|carry_out1 {} } { 0.000ns 0.000ns 1.735ns 0.564ns } { 0.000ns 1.036ns 0.879ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.170 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.843 ns) 0.843 ns reset 1 PIN PIN_F11 6 " "Info: 1: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = PIN_F11; Fanout = 6; PIN Node = 'reset'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.569 ns) + CELL(0.758 ns) 7.170 ns minute:u2\|carry_out1 2 REG LCFF_X15_Y32_N3 2 " "Info: 2: + IC(5.569 ns) + CELL(0.758 ns) = 7.170 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.327 ns" { reset minute:u2|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 22.33 % ) " "Info: Total cell delay = 1.601 ns ( 22.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.569 ns ( 77.67 % ) " "Info: Total interconnect delay = 5.569 ns ( 77.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.170 ns" { reset minute:u2|carry_out1 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "7.170 ns" { reset {} reset~combout {} minute:u2|carry_out1 {} } { 0.000ns 0.000ns 5.569ns } { 0.000ns 0.843ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.816 ns" { clk second:u1|carry_out1 minute:u2|carry_out1 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "4.816 ns" { clk {} clk~combout {} second:u1|carry_out1 {} minute:u2|carry_out1 {} } { 0.000ns 0.000ns 1.735ns 0.564ns } { 0.000ns 1.036ns 0.879ns 0.602ns } "" } } { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.170 ns" { reset minute:u2|carry_out1 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "7.170 ns" { reset {} reset~combout {} minute:u2|carry_out1 {} } { 0.000ns 0.000ns 5.569ns } { 0.000ns 0.843ns 0.758ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "118 " "Info: Allocated 118 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 20 00:08:54 2008 " "Info: Processing ended: Thu Nov 20 00:08:54 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}