topclock.tan.qmsg

VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "minute:u2\|carry_out1 " "Info: Detected ripple clock \"minute:u2\|carry_out1\" as buffer" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } } { "d:/studys/quartus/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/studys/quartus/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "minute:u2\|carry_out1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "second:u1\|carry_out1 " "Info: Detected ripple clock \"second:u1\|carry_out1\" as buffer" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 78 -1 0 } } { "d:/studys/quartus/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/studys/quartus/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "second:u1\|carry_out1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register minute:u2\|counter\[1\] register minute:u2\|carry_out1 244.56 MHz 4.089 ns Internal " "Info: Clock \"clk\" has Internal fmax of 244.56 MHz between source register \"minute:u2\|counter\[1\]\" and destination register \"minute:u2\|carry_out1\" (period= 4.089 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.454 ns + Longest register register " "Info: + Longest register to register delay is 1.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute:u2\|counter\[1\] 1 REG LCFF_X15_Y32_N19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y32_N19; Fanout = 4; REG Node = 'minute:u2\|counter\[1\]'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { minute:u2|counter[1] } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.521 ns) 0.897 ns minute:u2\|LessThan0~77 2 COMB LCCOMB_X15_Y32_N6 1 " "Info: 2: + IC(0.376 ns) + CELL(0.521 ns) = 0.897 ns; Loc. = LCCOMB_X15_Y32_N6; Fanout = 1; COMB Node = 'minute:u2\|LessThan0~77'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.897 ns" { minute:u2|counter[1] minute:u2|LessThan0~77 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/studys/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.177 ns) 1.358 ns minute:u2\|LessThan0~78 3 COMB LCCOMB_X15_Y32_N2 7 " "Info: 3: + IC(0.284 ns) + CELL(0.177 ns) = 1.358 ns; Loc. = LCCOMB_X15_Y32_N2; Fanout = 7; COMB Node = 'minute:u2\|LessThan0~78'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.461 ns" { minute:u2|LessThan0~77 minute:u2|LessThan0~78 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/studys/quartus/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.454 ns minute:u2\|carry_out1 4 REG LCFF_X15_Y32_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 1.454 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { minute:u2|LessThan0~78 minute:u2|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.794 ns ( 54.61 % ) " "Info: Total cell delay = 0.794 ns ( 54.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.660 ns ( 45.39 % ) " "Info: Total interconnect delay = 0.660 ns ( 45.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.454 ns" { minute:u2|counter[1] minute:u2|LessThan0~77 minute:u2|LessThan0~78 minute:u2|carry_out1 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "1.454 ns" { minute:u2|counter[1] {} minute:u2|LessThan0~77 {} minute:u2|LessThan0~78 {} minute:u2|carry_out1 {} } { 0.000ns 0.376ns 0.284ns 0.000ns } { 0.000ns 0.521ns 0.177ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.396 ns - Smallest " "Info: - Smallest clock skew is -2.396 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.816 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 4.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.735 ns) + CELL(0.879 ns) 3.650 ns second:u1\|carry_out1 2 REG LCFF_X16_Y32_N13 2 " "Info: 2: + IC(1.735 ns) + CELL(0.879 ns) = 3.650 ns; Loc. = LCFF_X16_Y32_N13; Fanout = 2; REG Node = 'second:u1\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { clk second:u1|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.602 ns) 4.816 ns minute:u2\|carry_out1 3 REG LCFF_X15_Y32_N3 2 " "Info: 3: + IC(0.564 ns) + CELL(0.602 ns) = 4.816 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.166 ns" { second:u1|carry_out1 minute:u2|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.517 ns ( 52.26 % ) " "Info: Total cell delay = 2.517 ns ( 52.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.299 ns ( 47.74 % ) " "Info: Total interconnect delay = 2.299 ns ( 47.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.816 ns" { clk second:u1|carry_out1 minute:u2|carry_out1 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "4.816 ns" { clk {} clk~combout {} second:u1|carry_out1 {} minute:u2|carry_out1 {} } { 0.000ns 0.000ns 1.735ns 0.564ns } { 0.000ns 1.036ns 0.879ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.212 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.212 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.735 ns) + CELL(0.879 ns) 3.650 ns second:u1\|carry_out1 2 REG LCFF_X16_Y32_N13 2 " "Info: 2: + IC(1.735 ns) + CELL(0.879 ns) = 3.650 ns; Loc. = LCFF_X16_Y32_N13; Fanout = 2; REG Node = 'second:u1\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { clk second:u1|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.855 ns) + CELL(0.000 ns) 5.505 ns second:u1\|carry_out1~clkctrl 3 COMB CLKCTRL_G9 6 " "Info: 3: + IC(1.855 ns) + CELL(0.000 ns) = 5.505 ns; Loc. = CLKCTRL_G9; Fanout = 6; COMB Node = 'second:u1\|carry_out1~clkctrl'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.855 ns" { second:u1|carry_out1 second:u1|carry_out1~clkctrl } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.105 ns) + CELL(0.602 ns) 7.212 ns minute:u2\|counter\[1\] 4 REG LCFF_X15_Y32_N19 4 " "Info: 4: + IC(1.105 ns) + CELL(0.602 ns) = 7.212 ns; Loc. = LCFF_X15_Y32_N19; Fanout = 4; REG Node = 'minute:u2\|counter\[1\]'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.707 ns" { second:u1|carry_out1~clkctrl minute:u2|counter[1] } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.517 ns ( 34.90 % ) " "Info: Total cell delay = 2.517 ns ( 34.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.695 ns ( 65.10 % ) " "Info: Total interconnect delay = 4.695 ns ( 65.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.212 ns" { clk second:u1|carry_out1 second:u1|carry_out1~clkctrl minute:u2|counter[1] } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "7.212 ns" { clk {} clk~combout {} second:u1|carry_out1 {} second:u1|carry_out1~clkctrl {} minute:u2|counter[1] {} } { 0.000ns 0.000ns 1.735ns 1.855ns 1.105ns } { 0.000ns 1.036ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.816 ns" { clk second:u1|carry_out1 minute:u2|carry_out1 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "4.816 ns" { clk {} clk~combout {} second:u1|carry_out1 {} minute:u2|carry_out1 {} } { 0.000ns 0.000ns 1.735ns 0.564ns } { 0.000ns 1.036ns 0.879ns 0.602ns } "" } } { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.212 ns" { clk second:u1|carry_out1 second:u1|carry_out1~clkctrl minute:u2|counter[1] } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "7.212 ns" { clk {} clk~combout {} second:u1|carry_out1 {} second:u1|carry_out1~clkctrl {} minute:u2|counter[1] {} } { 0.000ns 0.000ns 1.735ns 1.855ns 1.105ns } { 0.000ns 1.036ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.454 ns" { minute:u2|counter[1] minute:u2|LessThan0~77 minute:u2|LessThan0~78 minute:u2|carry_out1 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "1.454 ns" { minute:u2|counter[1] {} minute:u2|LessThan0~77 {} minute:u2|LessThan0~78 {} minute:u2|carry_out1 {} } { 0.000ns 0.376ns 0.284ns 0.000ns } { 0.000ns 0.521ns 0.177ns 0.096ns } "" } } { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.816 ns" { clk second:u1|carry_out1 minute:u2|carry_out1 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "4.816 ns" { clk {} clk~combout {} second:u1|carry_out1 {} minute:u2|carry_out1 {} } { 0.000ns 0.000ns 1.735ns 0.564ns } { 0.000ns 1.036ns 0.879ns 0.602ns } "" } } { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.212 ns" { clk second:u1|carry_out1 second:u1|carry_out1~clkctrl minute:u2|counter[1] } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "7.212 ns" { clk {} clk~combout {} second:u1|carry_out1 {} second:u1|carry_out1~clkctrl {} minute:u2|counter[1] {} } { 0.000ns 0.000ns 1.735ns 1.855ns 1.105ns } { 0.000ns 1.036ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "second:u1\|carry_out2 reset clk 3.864 ns register " "Info: tsu for register \"second:u1\|carry_out2\" (data pin = \"reset\", clock pin = \"clk\") is 3.864 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.821 ns + Longest pin register " "Info: + Longest pin to register delay is 6.821 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.843 ns) 0.843 ns reset 1 PIN PIN_F11 6 " "Info: 1: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = PIN_F11; Fanout = 6; PIN Node = 'reset'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.220 ns) + CELL(0.758 ns) 6.821 ns second:u1\|carry_out2 2 REG LCFF_X17_Y32_N17 1 " "Info: 2: + IC(5.220 ns) + CELL(0.758 ns) = 6.821 ns; Loc. = LCFF_X17_Y32_N17; Fanout = 1; REG Node = 'second:u1\|carry_out2'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.978 ns" { reset second:u1|carry_out2 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 23.47 % ) " "Info: Total cell delay = 1.601 ns ( 23.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.220 ns ( 76.53 % ) " "Info: Total interconnect delay = 5.220 ns ( 76.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.821 ns" { reset second:u1|carry_out2 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "6.821 ns" { reset {} reset~combout {} second:u1|carry_out2 {} } { 0.000ns 0.000ns 5.220ns } { 0.000ns 0.843ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 78 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.919 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.919 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.179 ns) + CELL(0.000 ns) 1.215 ns clk~clkctrl 2 COMB CLKCTRL_G3 7 " "Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.179 ns" { clk clk~clkctrl } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.602 ns) 2.919 ns second:u1\|carry_out2 3 REG LCFF_X17_Y32_N17 1 " "Info: 3: + IC(1.102 ns) + CELL(0.602 ns) = 2.919 ns; Loc. = LCFF_X17_Y32_N17; Fanout = 1; REG Node = 'second:u1\|carry_out2'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.704 ns" { clk~clkctrl second:u1|carry_out2 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 56.12 % ) " "Info: Total cell delay = 1.638 ns ( 56.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.281 ns ( 43.88 % ) " "Info: Total interconnect delay = 1.281 ns ( 43.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.919 ns" { clk clk~clkctrl second:u1|carry_out2 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "2.919 ns" { clk {} clk~combout {} clk~clkctrl {} second:u1|carry_out2 {} } { 0.000ns 0.000ns 0.179ns 1.102ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.821 ns" { reset second:u1|carry_out2 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "6.821 ns" { reset {} reset~combout {} second:u1|carry_out2 {} } { 0.000ns 0.000ns 5.220ns } { 0.000ns 0.843ns 0.758ns } "" } } { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.919 ns" { clk clk~clkctrl second:u1|carry_out2 } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "2.919 ns" { clk {} clk~combout {} clk~clkctrl {} second:u1|carry_out2 {} } { 0.000ns 0.000ns 0.179ns 1.102ns } { 0.000ns 1.036ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk houu\[3\] hour:u3\|counter\[3\] 12.978 ns register " "Info: tco from clock \"clk\" to destination pin \"houu\[3\]\" through register \"hour:u3\|counter\[3\]\" is 12.978 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.589 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.589 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns clk 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.735 ns) + CELL(0.879 ns) 3.650 ns second:u1\|carry_out1 2 REG LCFF_X16_Y32_N13 2 " "Info: 2: + IC(1.735 ns) + CELL(0.879 ns) = 3.650 ns; Loc. = LCFF_X16_Y32_N13; Fanout = 2; REG Node = 'second:u1\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { clk second:u1|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.879 ns) 5.093 ns minute:u2\|carry_out1 3 REG LCFF_X15_Y32_N3 2 " "Info: 3: + IC(0.564 ns) + CELL(0.879 ns) = 5.093 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2\|carry_out1'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.443 ns" { second:u1|carry_out1 minute:u2|carry_out1 } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.793 ns) + CELL(0.000 ns) 6.886 ns minute:u2\|carry_out1~clkctrl 4 COMB CLKCTRL_G10 5 " "Info: 4: + IC(1.793 ns) + CELL(0.000 ns) = 6.886 ns; Loc. = CLKCTRL_G10; Fanout = 5; COMB Node = 'minute:u2\|carry_out1~clkctrl'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.793 ns" { minute:u2|carry_out1 minute:u2|carry_out1~clkctrl } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.101 ns) + CELL(0.602 ns) 8.589 ns hour:u3\|counter\[3\] 5 REG LCFF_X43_Y35_N15 4 " "Info: 5: + IC(1.101 ns) + CELL(0.602 ns) = 8.589 ns; Loc. = LCFF_X43_Y35_N15; Fanout = 4; REG Node = 'hour:u3\|counter\[3\]'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.703 ns" { minute:u2|carry_out1~clkctrl hour:u3|counter[3] } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.396 ns ( 39.54 % ) " "Info: Total cell delay = 3.396 ns ( 39.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.193 ns ( 60.46 % ) " "Info: Total interconnect delay = 5.193 ns ( 60.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.589 ns" { clk second:u1|carry_out1 minute:u2|carry_out1 minute:u2|carry_out1~clkctrl hour:u3|counter[3] } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "8.589 ns" { clk {} clk~combout {} second:u1|carry_out1 {} minute:u2|carry_out1 {} minute:u2|carry_out1~clkctrl {} hour:u3|counter[3] {} } { 0.000ns 0.000ns 1.735ns 0.564ns 1.793ns 1.101ns } { 0.000ns 1.036ns 0.879ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.112 ns + Longest register pin " "Info: + Longest register to pin delay is 4.112 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour:u3\|counter\[3\] 1 REG LCFF_X43_Y35_N15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y35_N15; Fanout = 4; REG Node = 'hour:u3\|counter\[3\]'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { hour:u3|counter[3] } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.096 ns) + CELL(3.016 ns) 4.112 ns houu\[3\] 2 PIN PIN_A17 0 " "Info: 2: + IC(1.096 ns) + CELL(3.016 ns) = 4.112 ns; Loc. = PIN_A17; Fanout = 0; PIN Node = 'houu\[3\]'" {  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.112 ns" { hour:u3|counter[3] houu[3] } "NODE_NAME" } } { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.016 ns ( 73.35 % ) " "Info: Total cell delay = 3.016 ns ( 73.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.096 ns ( 26.65 % ) " "Info: Total interconnect delay = 1.096 ns ( 26.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.112 ns" { hour:u3|counter[3] houu[3] } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "4.112 ns" { hour:u3|counter[3] {} houu[3] {} } { 0.000ns 1.096ns } { 0.000ns 3.016ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.589 ns" { clk second:u1|carry_out1 minute:u2|carry_out1 minute:u2|carry_out1~clkctrl hour:u3|counter[3] } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "8.589 ns" { clk {} clk~combout {} second:u1|carry_out1 {} minute:u2|carry_out1 {} minute:u2|carry_out1~clkctrl {} hour:u3|counter[3] {} } { 0.000ns 0.000ns 1.735ns 0.564ns 1.793ns 1.101ns } { 0.000ns 1.036ns 0.879ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/studys/quartus/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.112 ns" { hour:u3|counter[3] houu[3] } "NODE_NAME" } } { "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/studys/quartus/altera/72/quartus/bin/Technology_Viewer.qrui" "4.112 ns" { hour:u3|counter[3] {} houu[3] {} } { 0.000ns 1.096ns } { 0.000ns 3.016ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}