topclock.map.rpt

VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.

; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; topclock.vhd                     ; yes             ; User VHDL File  ; D:/c/haoleba/topclock.vhd    ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 28    ;
;                                             ;       ;
; Total combinational functions               ; 28    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 4     ;
;     -- 3 input functions                    ; 2     ;
;     -- <=2 input functions                  ; 22    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 14    ;
;     -- arithmetic mode                      ; 14    ;
;                                             ;       ;
; Total registers                             ; 20    ;
;     -- Dedicated logic registers            ; 20    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 36    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 8     ;
; Total fan-out                               ; 158   ;
; Average fan-out                             ; 1.88  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |topclock                  ; 28 (1)            ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 36   ; 0            ; |topclock           ; work         ;
;    |hour:u3|               ; 8 (8)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |topclock|hour:u3   ; work         ;
;    |minute:u2|             ; 9 (9)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |topclock|minute:u2 ; work         ;
;    |second:u1|             ; 10 (10)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |topclock|second:u1 ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 20    ;
; Number of registers using Synchronous Clear  ; 17    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 17    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 3     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 20 00:08:25 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off topclock -c topclock
Info: Found 10 design units, including 5 entities, in source file topclock.vhd
    Info: Found design unit 1: topclock-one
    Info: Found design unit 2: second-behav
    Info: Found design unit 3: minute-behav
    Info: Found design unit 4: hour-behav
    Info: Found design unit 5: alar-a
    Info: Found entity 1: topclock
    Info: Found entity 2: second
    Info: Found entity 3: minute
    Info: Found entity 4: hour
    Info: Found entity 5: alar
Info: Elaborating entity "topclock" for the top level hierarchy
Info: Elaborating entity "second" for hierarchy "second:u1"
Warning (10492): VHDL Process Statement warning at topclock.vhd(95): signal "cles" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "minute" for hierarchy "minute:u2"
Warning (10492): VHDL Process Statement warning at topclock.vhd(129): signal "clem" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "hour" for hierarchy "hour:u3"
Warning (10492): VHDL Process Statement warning at topclock.vhd(162): signal "cleh" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "alar" for hierarchy "alar:u4"
Warning (10492): VHDL Process Statement warning at topclock.vhd(188): signal "setm" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at topclock.vhd(188): signal "minu1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at topclock.vhd(188): signal "seth" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at topclock.vhd(188): signal "houu1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at topclock.vhd(194): signal "al" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at topclock.vhd(184): inferring latch(es) for signal or variable "al", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "al" at topclock.vhd(184)
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "alarm" stuck at GND
Warning: Design contains 12 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "enable"
    Warning (15610): No output dependent on input pin "setm[0]"
    Warning (15610): No output dependent on input pin "setm[1]"
    Warning (15610): No output dependent on input pin "setm[2]"
    Warning (15610): No output dependent on input pin "setm[3]"
    Warning (15610): No output dependent on input pin "setm[4]"
    Warning (15610): No output dependent on input pin "setm[5]"
    Warning (15610): No output dependent on input pin "seth[0]"
    Warning (15610): No output dependent on input pin "seth[1]"
    Warning (15610): No output dependent on input pin "seth[2]"
    Warning (15610): No output dependent on input pin "seth[3]"
    Warning (15610): No output dependent on input pin "seth[4]"
Info: Implemented 66 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 19 output pins
    Info: Implemented 30 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Allocated 163 megabytes of memory during processing
    Info: Processing ended: Thu Nov 20 00:08:28 2008
    Info: Elapsed time: 00:00:03