topclock.tan.rpt

VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.

; N/A   ; None         ; 12.610 ns  ; hour:u3|counter[0]   ; houu[0] ; clk        ;
; N/A   ; None         ; 11.667 ns  ; minute:u2|counter[5] ; minu[5] ; clk        ;
; N/A   ; None         ; 11.641 ns  ; minute:u2|counter[2] ; minu[2] ; clk        ;
; N/A   ; None         ; 11.401 ns  ; minute:u2|counter[1] ; minu[1] ; clk        ;
; N/A   ; None         ; 11.348 ns  ; minute:u2|counter[3] ; minu[3] ; clk        ;
; N/A   ; None         ; 11.340 ns  ; minute:u2|counter[0] ; minu[0] ; clk        ;
; N/A   ; None         ; 11.330 ns  ; minute:u2|counter[4] ; minu[4] ; clk        ;
; N/A   ; None         ; 10.093 ns  ; minute:u2|carry_out1 ; baoshi  ; clk        ;
; N/A   ; None         ; 8.322 ns   ; second:u1|carry_out2 ; baoshi  ; clk        ;
; N/A   ; None         ; 7.610 ns   ; second:u1|counter[1] ; seco[1] ; clk        ;
; N/A   ; None         ; 7.589 ns   ; second:u1|counter[4] ; seco[4] ; clk        ;
; N/A   ; None         ; 7.367 ns   ; second:u1|counter[2] ; seco[2] ; clk        ;
; N/A   ; None         ; 7.315 ns   ; second:u1|counter[3] ; seco[3] ; clk        ;
; N/A   ; None         ; 7.072 ns   ; second:u1|counter[5] ; seco[5] ; clk        ;
; N/A   ; None         ; 7.047 ns   ; second:u1|counter[0] ; seco[0] ; clk        ;
+-------+--------------+------------+----------------------+---------+------------+


+-----------------------------------------------------------------------------------+
; th                                                                                ;
+---------------+-------------+-----------+-------+----------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To                   ; To Clock ;
+---------------+-------------+-----------+-------+----------------------+----------+
; N/A           ; None        ; -2.068 ns ; reset ; minute:u2|carry_out1 ; clk      ;
; N/A           ; None        ; -3.412 ns ; reset ; second:u1|carry_out1 ; clk      ;
; N/A           ; None        ; -3.616 ns ; reset ; second:u1|carry_out2 ; clk      ;
+---------------+-------------+-----------+-------+----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 20 00:08:53 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off topclock -c topclock --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "minute:u2|carry_out1" as buffer
    Info: Detected ripple clock "second:u1|carry_out1" as buffer
Info: Clock "clk" has Internal fmax of 244.56 MHz between source register "minute:u2|counter[1]" and destination register "minute:u2|carry_out1" (period= 4.089 ns)
    Info: + Longest register to register delay is 1.454 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y32_N19; Fanout = 4; REG Node = 'minute:u2|counter[1]'
        Info: 2: + IC(0.376 ns) + CELL(0.521 ns) = 0.897 ns; Loc. = LCCOMB_X15_Y32_N6; Fanout = 1; COMB Node = 'minute:u2|LessThan0~77'
        Info: 3: + IC(0.284 ns) + CELL(0.177 ns) = 1.358 ns; Loc. = LCCOMB_X15_Y32_N2; Fanout = 7; COMB Node = 'minute:u2|LessThan0~78'
        Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 1.454 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2|carry_out1'
        Info: Total cell delay = 0.794 ns ( 54.61 % )
        Info: Total interconnect delay = 0.660 ns ( 45.39 % )
    Info: - Smallest clock skew is -2.396 ns
        Info: + Shortest clock path from clock "clk" to destination register is 4.816 ns
            Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(1.735 ns) + CELL(0.879 ns) = 3.650 ns; Loc. = LCFF_X16_Y32_N13; Fanout = 2; REG Node = 'second:u1|carry_out1'
            Info: 3: + IC(0.564 ns) + CELL(0.602 ns) = 4.816 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2|carry_out1'
            Info: Total cell delay = 2.517 ns ( 52.26 % )
            Info: Total interconnect delay = 2.299 ns ( 47.74 % )
        Info: - Longest clock path from clock "clk" to source register is 7.212 ns
            Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(1.735 ns) + CELL(0.879 ns) = 3.650 ns; Loc. = LCFF_X16_Y32_N13; Fanout = 2; REG Node = 'second:u1|carry_out1'
            Info: 3: + IC(1.855 ns) + CELL(0.000 ns) = 5.505 ns; Loc. = CLKCTRL_G9; Fanout = 6; COMB Node = 'second:u1|carry_out1~clkctrl'
            Info: 4: + IC(1.105 ns) + CELL(0.602 ns) = 7.212 ns; Loc. = LCFF_X15_Y32_N19; Fanout = 4; REG Node = 'minute:u2|counter[1]'
            Info: Total cell delay = 2.517 ns ( 34.90 % )
            Info: Total interconnect delay = 4.695 ns ( 65.10 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Micro setup delay of destination is -0.038 ns
Info: tsu for register "second:u1|carry_out2" (data pin = "reset", clock pin = "clk") is 3.864 ns
    Info: + Longest pin to register delay is 6.821 ns
        Info: 1: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = PIN_F11; Fanout = 6; PIN Node = 'reset'
        Info: 2: + IC(5.220 ns) + CELL(0.758 ns) = 6.821 ns; Loc. = LCFF_X17_Y32_N17; Fanout = 1; REG Node = 'second:u1|carry_out2'
        Info: Total cell delay = 1.601 ns ( 23.47 % )
        Info: Total interconnect delay = 5.220 ns ( 76.53 % )
    Info: + Micro setup delay of destination is -0.038 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.919 ns
        Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.179 ns) + CELL(0.000 ns) = 1.215 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.102 ns) + CELL(0.602 ns) = 2.919 ns; Loc. = LCFF_X17_Y32_N17; Fanout = 1; REG Node = 'second:u1|carry_out2'
        Info: Total cell delay = 1.638 ns ( 56.12 % )
        Info: Total interconnect delay = 1.281 ns ( 43.88 % )
Info: tco from clock "clk" to destination pin "houu[3]" through register "hour:u3|counter[3]" is 12.978 ns
    Info: + Longest clock path from clock "clk" to source register is 8.589 ns
        Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.735 ns) + CELL(0.879 ns) = 3.650 ns; Loc. = LCFF_X16_Y32_N13; Fanout = 2; REG Node = 'second:u1|carry_out1'
        Info: 3: + IC(0.564 ns) + CELL(0.879 ns) = 5.093 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2|carry_out1'
        Info: 4: + IC(1.793 ns) + CELL(0.000 ns) = 6.886 ns; Loc. = CLKCTRL_G10; Fanout = 5; COMB Node = 'minute:u2|carry_out1~clkctrl'
        Info: 5: + IC(1.101 ns) + CELL(0.602 ns) = 8.589 ns; Loc. = LCFF_X43_Y35_N15; Fanout = 4; REG Node = 'hour:u3|counter[3]'
        Info: Total cell delay = 3.396 ns ( 39.54 % )
        Info: Total interconnect delay = 5.193 ns ( 60.46 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 4.112 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y35_N15; Fanout = 4; REG Node = 'hour:u3|counter[3]'
        Info: 2: + IC(1.096 ns) + CELL(3.016 ns) = 4.112 ns; Loc. = PIN_A17; Fanout = 0; PIN Node = 'houu[3]'
        Info: Total cell delay = 3.016 ns ( 73.35 % )
        Info: Total interconnect delay = 1.096 ns ( 26.65 % )
Info: th for register "minute:u2|carry_out1" (data pin = "reset", clock pin = "clk") is -2.068 ns
    Info: + Longest clock path from clock "clk" to destination register is 4.816 ns
        Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.735 ns) + CELL(0.879 ns) = 3.650 ns; Loc. = LCFF_X16_Y32_N13; Fanout = 2; REG Node = 'second:u1|carry_out1'
        Info: 3: + IC(0.564 ns) + CELL(0.602 ns) = 4.816 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2|carry_out1'
        Info: Total cell delay = 2.517 ns ( 52.26 % )
        Info: Total interconnect delay = 2.299 ns ( 47.74 % )
    Info: + Micro hold delay of destination is 0.286 ns
    Info: - Shortest pin to register delay is 7.170 ns
        Info: 1: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = PIN_F11; Fanout = 6; PIN Node = 'reset'
        Info: 2: + IC(5.569 ns) + CELL(0.758 ns) = 7.170 ns; Loc. = LCFF_X15_Y32_N3; Fanout = 2; REG Node = 'minute:u2|carry_out1'
        Info: Total cell delay = 1.601 ns ( 22.33 % )
        Info: Total interconnect delay = 5.569 ns ( 77.67 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 118 megabytes of memory during processing
    Info: Processing ended: Thu Nov 20 00:08:54 2008
    Info: Elapsed time: 00:00:01