sram_test.v

使用Verilog写的SRAM的控制程序

`timescale 1ns / 1ps
//在硬件中测试sram，从拨码开关和按键输入，led输出


module sram_test(clk,rst,data,addr,ub,lb,ce,we,oe,data_in,data_out);
 input               clk     ; 
 input               rst     ;
 input   [15:0]      data_in ;
 
 inout   [15:0]      data    ;
 
 output  [15:0]      data_out;
 output  [17:0]      addr    ;
 output              ub      ;
 output              lb      ;
 output              ce      ;
 output              we      ;
 output              oe      ;
 
 reg      [17:0]     addr    ;
 reg      [15:0]     data_out;
 reg      [15:0]     data_reg;
 wire     [15:0]     data    ;
 wire                ub      ;
 wire                lb      ;
 reg                 ce      ;
 reg                 we      ;
 reg                 oe      ;
 
 reg      [3 :0]     state   ;
 
 parameter     s1 = 4'b0001,           //write setup & read finish
 					s2 = 4'b0010,				//write setup ready
					s3 = 4'b0100,           //read setup & write finish
					s4 = 4'b1000;           //read

assign     ub = 0;
assign     lb = 0;
assign     data =(oe&we)? data_reg : 16'hzzzz;

always @ ( posedge clk or negedge rst )
	if ( !rst )
		begin
			state<=s1;
			oe<=1;
			ce<=0;
			we<=1;
			addr<=0;
		end
	else
		begin
			case ( state )	  
			s1:	begin
						 we<=1;
						 oe<=1;						 
						 state<=s2;						 
					end 			
			s2: 	begin
						we<=0;
						oe<=1;
						state<=s3;
						addr<=addr+1;
						data_reg<=data_in;
					end  
			s3:	begin
						we<=1;
						oe<=1;
						//data_reg<=16'hzzzz;
						state<=s4;
					end	 
			s4:	begin
						we<=1;
						oe<=0;
						data_out<=data;
						state<=s1;
					end	  			
			default: state<=s1;	  
			endcase
		end
endmodule