📄 reg16b.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\electronics\muxflie\dds_vhdl\reg16b.rpt
reg16b
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 2/ 48( 4%) 3/ 48( 6%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
B: 5/ 96( 5%) 4/ 48( 8%) 0/ 48( 0%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 4/ 96( 4%) 3/ 48( 6%) 2/ 48( 4%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\electronics\muxflie\dds_vhdl\reg16b.rpt
reg16b
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 load
Device-Specific Information: e:\electronics\muxflie\dds_vhdl\reg16b.rpt
reg16b
** EQUATIONS **
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
din4 : INPUT;
din5 : INPUT;
din6 : INPUT;
din7 : INPUT;
din8 : INPUT;
din9 : INPUT;
din10 : INPUT;
din11 : INPUT;
din12 : INPUT;
din13 : INPUT;
din14 : INPUT;
din15 : INPUT;
load : INPUT;
-- Node name is 'dout0'
-- Equation name is 'dout0', type is output
dout0 = _LC1_C23;
-- Node name is 'dout1'
-- Equation name is 'dout1', type is output
dout1 = _LC5_A13;
-- Node name is 'dout2'
-- Equation name is 'dout2', type is output
dout2 = _LC1_C7;
-- Node name is 'dout3'
-- Equation name is 'dout3', type is output
dout3 = _LC5_C3;
-- Node name is 'dout4'
-- Equation name is 'dout4', type is output
dout4 = _LC4_B11;
-- Node name is 'dout5'
-- Equation name is 'dout5', type is output
dout5 = _LC7_C21;
-- Node name is 'dout6'
-- Equation name is 'dout6', type is output
dout6 = _LC1_B8;
-- Node name is 'dout7'
-- Equation name is 'dout7', type is output
dout7 = _LC4_A21;
-- Node name is 'dout8'
-- Equation name is 'dout8', type is output
dout8 = _LC8_A12;
-- Node name is 'dout9'
-- Equation name is 'dout9', type is output
dout9 = _LC7_C11;
-- Node name is 'dout10'
-- Equation name is 'dout10', type is output
dout10 = _LC5_B10;
-- Node name is 'dout11'
-- Equation name is 'dout11', type is output
dout11 = _LC7_B18;
-- Node name is 'dout12'
-- Equation name is 'dout12', type is output
dout12 = _LC8_B2;
-- Node name is 'dout13'
-- Equation name is 'dout13', type is output
dout13 = _LC3_A17;
-- Node name is 'dout14'
-- Equation name is 'dout14', type is output
dout14 = _LC8_C24;
-- Node name is 'dout15'
-- Equation name is 'dout15', type is output
dout15 = _LC3_A1;
-- Node name is ':18'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( din15, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':20'
-- Equation name is '_LC8_C24', type is buried
_LC8_C24 = DFFE( din14, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':22'
-- Equation name is '_LC3_A17', type is buried
_LC3_A17 = DFFE( din13, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':24'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = DFFE( din12, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':26'
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = DFFE( din11, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':28'
-- Equation name is '_LC5_B10', type is buried
_LC5_B10 = DFFE( din10, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':30'
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = DFFE( din9, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':32'
-- Equation name is '_LC8_A12', type is buried
_LC8_A12 = DFFE( din8, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':34'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = DFFE( din7, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':36'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = DFFE( din6, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':38'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = DFFE( din5, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':40'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = DFFE( din4, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':42'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = DFFE( din3, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':44'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = DFFE( din2, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':46'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = DFFE( din1, GLOBAL( load), VCC, VCC, VCC);
-- Node name is ':48'
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = DFFE( din0, GLOBAL( load), VCC, VCC, VCC);
Project Information e:\electronics\muxflie\dds_vhdl\reg16b.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,597K
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