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📄 dds_vhdl.rpt

📁 基于FPGA的直接数字频率合成器(DDS)设计 (源程序)
💻 RPT
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         #  _LC3_A6 & !_LC6_A12 & !pword5
         #  _LC3_A6 &  _LC6_A12 &  pword5
         # !_LC3_A6 &  _LC6_A12 & !pword5;

-- Node name is '|reg8b:u5|:16' 
-- Equation name is '_LC4_A12', type is buried 
_LC4_A12 = DFFE( _EQ016,  clk,  VCC,  VCC,  VCC);
  _EQ016 = !_LC2_A6 & !_LC5_A3 &  pword4
         #  _LC2_A6 & !_LC5_A3 & !pword4
         #  _LC2_A6 &  _LC5_A3 &  pword4
         # !_LC2_A6 &  _LC5_A3 & !pword4;

-- Node name is '|reg8b:u5|:18' 
-- Equation name is '_LC3_A3', type is buried 
_LC3_A3  = DFFE( _EQ017,  clk,  VCC,  VCC,  VCC);
  _EQ017 = !_LC1_A3 & !_LC2_A3 &  pword3
         # !_LC1_A3 &  _LC2_A3 & !pword3
         #  _LC1_A3 &  _LC2_A3 &  pword3
         #  _LC1_A3 & !_LC2_A3 & !pword3;

-- Node name is '|reg8b:u5|:20' 
-- Equation name is '_LC6_A3', type is buried 
_LC6_A3  = DFFE( _EQ018,  clk,  VCC,  VCC,  VCC);
  _EQ018 = !_LC5_A4 & !_LC6_A4 &  pword2
         #  _LC5_A4 & !_LC6_A4 & !pword2
         #  _LC5_A4 &  _LC6_A4 &  pword2
         # !_LC5_A4 &  _LC6_A4 & !pword2;

-- Node name is '|reg8b:u5|:22' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = DFFE( _EQ019,  clk,  VCC,  VCC,  VCC);
  _EQ019 =  _LC3_A4 & !_LC7_A4 &  pword0 & !pword1
         # !_LC7_A4 & !pword0 &  pword1
         # !_LC3_A4 & !_LC7_A4 &  pword1
         #  _LC3_A4 &  _LC7_A4 &  pword0 &  pword1
         #  _LC7_A4 & !pword0 & !pword1
         # !_LC3_A4 &  _LC7_A4 & !pword1;

-- Node name is '|reg8b:u5|:24' 
-- Equation name is '_LC8_A4', type is buried 
_LC8_A4  = DFFE( _EQ020,  clk,  VCC,  VCC,  VCC);
  _EQ020 = !_LC3_A4 &  pword0
         #  _LC3_A4 & !pword0;

-- Node name is '|reg16b:u2|:18' 
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = DFFE( _EQ021,  clk,  VCC,  VCC,  VCC);
  _EQ021 =  fword7 &  _LC1_A6 &  _LC7_A6
         # !fword7 & !_LC1_A6 &  _LC7_A6
         # !fword7 &  _LC1_A6 & !_LC7_A6
         #  fword7 & !_LC1_A6 & !_LC7_A6;

-- Node name is '|reg16b:u2|:20' 
-- Equation name is '_LC4_A6', type is buried 
_LC4_A6  = DFFE( _EQ022,  clk,  VCC,  VCC,  VCC);
  _EQ022 = !fword6 &  _LC4_A6 & !_LC6_A6
         #  fword6 & !_LC4_A6 & !_LC6_A6
         #  fword6 &  _LC4_A6 &  _LC6_A6
         # !fword6 & !_LC4_A6 &  _LC6_A6;

-- Node name is '|reg16b:u2|:22' 
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = DFFE( _EQ023,  clk,  VCC,  VCC,  VCC);
  _EQ023 = !fword5 &  _LC3_A6 & !_LC5_A6
         #  fword5 & !_LC3_A6 & !_LC5_A6
         #  fword5 &  _LC3_A6 &  _LC5_A6
         # !fword5 & !_LC3_A6 &  _LC5_A6;

-- Node name is '|reg16b:u2|:24' 
-- Equation name is '_LC2_A6', type is buried 
_LC2_A6  = DFFE( _EQ024,  clk,  VCC,  VCC,  VCC);
  _EQ024 = !fword4 &  _LC2_A6 & !_LC8_A3
         #  fword4 & !_LC2_A6 & !_LC8_A3
         #  fword4 &  _LC2_A6 &  _LC8_A3
         # !fword4 & !_LC2_A6 &  _LC8_A3;

-- Node name is '|reg16b:u2|:26' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = DFFE( _EQ025,  clk,  VCC,  VCC,  VCC);
  _EQ025 = !fword3 &  _LC2_A3 & !_LC4_A4
         #  fword3 & !_LC2_A3 & !_LC4_A4
         #  fword3 &  _LC2_A3 &  _LC4_A4
         # !fword3 & !_LC2_A3 &  _LC4_A4;

-- Node name is '|reg16b:u2|:28' 
-- Equation name is '_LC5_A4', type is buried 
_LC5_A4  = DFFE( _EQ026,  clk,  VCC,  VCC,  VCC);
  _EQ026 = !fword2 & !_LC1_A4 &  _LC5_A4
         #  fword2 & !_LC1_A4 & !_LC5_A4
         #  fword2 &  _LC1_A4 &  _LC5_A4
         # !fword2 &  _LC1_A4 & !_LC5_A4;

-- Node name is '|reg16b:u2|:30' 
-- Equation name is '_LC7_A4', type is buried 
_LC7_A4  = DFFE( _EQ027,  clk,  VCC,  VCC,  VCC);
  _EQ027 =  fword0 &  fword1 &  _LC3_A4 &  _LC7_A4
         # !fword1 & !_LC3_A4 &  _LC7_A4
         # !fword0 & !fword1 &  _LC7_A4
         #  fword0 & !fword1 &  _LC3_A4 & !_LC7_A4
         #  fword1 & !_LC3_A4 & !_LC7_A4
         # !fword0 &  fword1 & !_LC7_A4;

-- Node name is '|reg16b:u2|:32' 
-- Equation name is '_LC3_A4', type is buried 
_LC3_A4  = DFFE( _EQ028,  clk,  VCC,  VCC,  VCC);
  _EQ028 = !fword0 &  _LC3_A4
         #  fword0 & !_LC3_A4;

-- Node name is '|sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC3_C', type is memory 
_EC3_C   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC8_A4, _LC2_A4, _LC6_A3, _LC3_A3, _LC4_A12, _LC2_A12, _LC1_A12, _LC3_A12, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_C', type is memory 
_EC2_C   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC8_A4, _LC2_A4, _LC6_A3, _LC3_A3, _LC4_A12, _LC2_A12, _LC1_A12, _LC3_A12, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC7_C', type is memory 
_EC7_C   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC8_A4, _LC2_A4, _LC6_A3, _LC3_A3, _LC4_A12, _LC2_A12, _LC1_A12, _LC3_A12, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC6_C', type is memory 
_EC6_C   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC8_A4, _LC2_A4, _LC6_A3, _LC3_A3, _LC4_A12, _LC2_A12, _LC1_A12, _LC3_A12, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_C', type is memory 
_EC1_C   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC8_A4, _LC2_A4, _LC6_A3, _LC3_A3, _LC4_A12, _LC2_A12, _LC1_A12, _LC3_A12, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_C', type is memory 
_EC4_C   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC8_A4, _LC2_A4, _LC6_A3, _LC3_A3, _LC4_A12, _LC2_A12, _LC1_A12, _LC3_A12, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC8_C', type is memory 
_EC8_C   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC8_A4, _LC2_A4, _LC6_A3, _LC3_A3, _LC4_A12, _LC2_A12, _LC1_A12, _LC3_A12, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC5_C', type is memory 
_EC5_C   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC8_A4, _LC2_A4, _LC6_A3, _LC3_A3, _LC4_A12, _LC2_A12, _LC1_A12, _LC3_A12, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_A', type is memory 
_EC4_A   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC3_A4, _LC7_A4, _LC5_A4, _LC2_A3, _LC2_A6, _LC3_A6, _LC4_A6, _LC1_A6, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC6_A', type is memory 
_EC6_A   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC3_A4, _LC7_A4, _LC5_A4, _LC2_A3, _LC2_A6, _LC3_A6, _LC4_A6, _LC1_A6, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_A', type is memory 
_EC1_A   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC3_A4, _LC7_A4, _LC5_A4, _LC2_A3, _LC2_A6, _LC3_A6, _LC4_A6, _LC1_A6, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC8_A', type is memory 
_EC8_A   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC3_A4, _LC7_A4, _LC5_A4, _LC2_A3, _LC2_A6, _LC3_A6, _LC4_A6, _LC1_A6, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_A', type is memory 
_EC2_A   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC3_A4, _LC7_A4, _LC5_A4, _LC2_A3, _LC2_A6, _LC3_A6, _LC4_A6, _LC1_A6, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC7_A', type is memory 
_EC7_A   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC3_A4, _LC7_A4, _LC5_A4, _LC2_A3, _LC2_A6, _LC3_A6, _LC4_A6, _LC1_A6, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC5_A', type is memory 
_EC5_A   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC3_A4, _LC7_A4, _LC5_A4, _LC2_A3, _LC2_A6, _LC3_A6, _LC4_A6, _LC1_A6, VCC, VCC, VCC,);

-- Node name is '|sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC3_A', type is memory 
_EC3_A   = MEMORY_SEGMENT( VCC, clk, VCC, GND, VCC, _LC3_A4, _LC7_A4, _LC5_A4, _LC2_A3, _LC2_A6, _LC3_A6, _LC4_A6, _LC1_A6, VCC, VCC, VCC,);



Project Information                                   e:\dds_vhdl\dds_vhdl.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,770K

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