📄 dds_vhdl.rpt
字号:
C18 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C19 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 3/8 ( 37%) 5/8 ( 62%) 1/2 2/2 9/22( 40%)
C25 8/8 (100%) 0/8 ( 0%) 8/8 (100%) 1/2 2/2 9/22( 40%)
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 31/53 ( 58%)
Total logic cells used: 44/576 ( 7%)
Total embedded cells used: 16/24 ( 66%)
Total EABs used: 2/3 ( 66%)
Average fan-in: 2.31/4 ( 57%)
Total fan-in: 102/2304 ( 4%)
Total input pins required: 17
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 44
Total flipflops required: 16
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Logic cells inserted for fitting: 16
Synthesized logic cells: 17/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 6 8 0 7 0 0 0 0 0 7 8 0 1 2 1 0 0 0 1 0 0 0 0 33/8
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 3/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 1 0 0 1 1 1 1 1 1 1 0 8/8
Total: 0 0 6 8 0 7 0 0 0 0 0 7 16 0 3 3 1 1 1 2 2 1 1 1 0 44/16
Device-Specific Information: e:\dds_vhdl\dds_vhdl.rpt
dds_vhdl
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
78 - - - 24 INPUT 0 0 0 32 clk
1 - - - -- INPUT 0 0 0 3 fword0
2 - - - -- INPUT 0 0 0 2 fword1
3 - - - 12 INPUT 0 0 0 2 fword2
5 - - - 05 INPUT 0 0 0 2 fword3
6 - - - 04 INPUT 0 0 0 2 fword4
7 - - - 03 INPUT 0 0 0 2 fword5
8 - - - 03 INPUT 0 0 0 2 fword6
9 - - - 02 INPUT 0 0 0 1 fword7
10 - - - 01 INPUT 0 0 0 3 pword0
11 - - - 01 INPUT 0 0 0 2 pword1
16 - - A -- INPUT 0 0 0 2 pword2
17 - - A -- INPUT 0 0 0 2 pword3
18 - - A -- INPUT 0 0 0 2 pword4
19 - - A -- INPUT 0 0 0 2 pword5
21 - - B -- INPUT 0 0 0 2 pword6
22 - - B -- INPUT 0 0 0 1 pword7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\dds_vhdl\dds_vhdl.rpt
dds_vhdl
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
50 - - - 17 OUTPUT 0 1 0 0 fout0
51 - - - 18 OUTPUT 0 1 0 0 fout1
52 - - - 19 OUTPUT 0 1 0 0 fout2
53 - - - 20 OUTPUT 0 1 0 0 fout3
54 - - - 21 OUTPUT 0 1 0 0 fout4
58 - - C -- OUTPUT 0 1 0 0 fout5
59 - - C -- OUTPUT 0 1 0 0 fout6
60 - - C -- OUTPUT 0 1 0 0 fout7
64 - - B -- OUTPUT 0 1 0 0 pout0
65 - - B -- OUTPUT 0 1 0 0 pout1
66 - - B -- OUTPUT 0 1 0 0 pout2
67 - - B -- OUTPUT 0 1 0 0 pout3
69 - - A -- OUTPUT 0 1 0 0 pout4
70 - - A -- OUTPUT 0 1 0 0 pout5
71 - - A -- OUTPUT 0 1 0 0 pout6
72 - - A -- OUTPUT 0 1 0 0 pout7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\dds_vhdl\dds_vhdl.rpt
dds_vhdl
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 04 OR2 2 2 0 2 |adder8b:u4|LPM_ADD_SUB:25|addcore:adder|pcarry1
- 1 - A 03 OR2 1 2 0 2 |adder8b:u4|LPM_ADD_SUB:25|addcore:adder|pcarry2
- 5 - A 03 OR2 1 2 0 2 |adder8b:u4|LPM_ADD_SUB:25|addcore:adder|pcarry3
- 6 - A 12 OR2 1 2 0 2 |adder8b:u4|LPM_ADD_SUB:25|addcore:adder|pcarry4
- 7 - A 12 OR2 1 2 0 2 |adder8b:u4|LPM_ADD_SUB:25|addcore:adder|pcarry5
- 5 - A 12 OR2 s 1 1 0 1 |adder8b:u4|LPM_ADD_SUB:25|addcore:adder|~162~1
- 1 - A 04 OR2 2 2 0 2 |adder16b:u1|LPM_ADD_SUB:49|addcore:adder|pcarry9
- 4 - A 04 OR2 1 2 0 2 |adder16b:u1|LPM_ADD_SUB:49|addcore:adder|pcarry10
- 8 - A 03 OR2 1 2 0 2 |adder16b:u1|LPM_ADD_SUB:49|addcore:adder|pcarry11
- 5 - A 06 OR2 1 2 0 2 |adder16b:u1|LPM_ADD_SUB:49|addcore:adder|pcarry12
- 6 - A 06 OR2 1 2 0 2 |adder16b:u1|LPM_ADD_SUB:49|addcore:adder|pcarry13
- 7 - A 06 OR2 1 2 0 1 |adder16b:u1|LPM_ADD_SUB:49|addcore:adder|pcarry14
- 2 - C 18 SOFT s r 0 1 1 0 fout0~fit~in1
- 1 - C 17 SOFT s r 0 1 1 0 fout1~fit~in1
- 2 - C 19 SOFT s r 0 1 1 0 fout2~fit~in1
- 2 - C 20 SOFT s r 0 1 1 0 fout3~fit~in1
- 1 - C 21 SOFT s r 0 1 1 0 fout4~fit~in1
- 7 - C 23 SOFT s r 0 1 1 0 fout5~fit~in1
- 8 - C 14 SOFT s r 0 1 1 0 fout6~fit~in1
- 4 - C 22 SOFT s r 0 1 1 0 fout7~fit~in1
- 6 - B 14 SOFT s r 0 1 1 0 pout0~fit~in1
- 5 - B 19 SOFT s r 0 1 1 0 pout1~fit~in1
- 3 - A 16 SOFT s r 0 1 1 0 pout2~fit~in1
- 1 - B 15 SOFT s r 0 1 1 0 pout3~fit~in1
- 8 - A 14 SOFT s r 0 1 1 0 pout4~fit~in1
- 8 - A 20 SOFT s r 0 1 1 0 pout5~fit~in1
- 4 - A 15 SOFT s r 0 1 1 0 pout6~fit~in1
- 3 - A 15 SOFT s r 0 1 1 0 pout7~fit~in1
- 3 - A 12 DFFE 2 3 0 8 |reg8b:u5|:10
- 1 - A 12 DFFE 2 2 0 8 |reg8b:u5|:12
- 2 - A 12 DFFE 2 2 0 8 |reg8b:u5|:14
- 4 - A 12 DFFE 2 2 0 8 |reg8b:u5|:16
- 3 - A 03 DFFE 2 2 0 8 |reg8b:u5|:18
- 6 - A 03 DFFE 2 2 0 8 |reg8b:u5|:20
- 2 - A 04 DFFE 3 2 0 8 |reg8b:u5|:22
- 8 - A 04 DFFE 2 1 0 8 |reg8b:u5|:24
- 1 - A 06 DFFE 2 1 0 9 |reg16b:u2|:18
- 4 - A 06 DFFE 2 1 0 11 |reg16b:u2|:20
- 3 - A 06 DFFE 2 1 0 11 |reg16b:u2|:22
- 2 - A 06 DFFE 2 1 0 11 |reg16b:u2|:24
- 2 - A 03 DFFE 2 1 0 11 |reg16b:u2|:26
- 5 - A 04 DFFE 2 1 0 11 |reg16b:u2|:28
- 7 - A 04 DFFE 3 1 0 11 |reg16b:u2|:30
- 3 - A 04 DFFE 2 0 0 13 |reg16b:u2|:32
- - 3 C -- MEM_SGMT 1 8 0 1 |sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 2 C -- MEM_SGMT 1 8 0 1 |sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 7 C -- MEM_SGMT 1 8 0 1 |sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 6 C -- MEM_SGMT 1 8 0 1 |sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 1 C -- MEM_SGMT 1 8 0 1 |sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 4 C -- MEM_SGMT 1 8 0 1 |sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 8 C -- MEM_SGMT 1 8 0 1 |sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 5 C -- MEM_SGMT 1 8 0 1 |sin_rom:u3|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- - 4 A -- MEM_SGMT 1 8 0 1 |sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 6 A -- MEM_SGMT 1 8 0 1 |sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 1 A -- MEM_SGMT 1 8 0 1 |sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 8 A -- MEM_SGMT 1 8 0 1 |sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 2 A -- MEM_SGMT 1 8 0 1 |sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 7 A -- MEM_SGMT 1 8 0 1 |sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 5 A -- MEM_SGMT 1 8 0 1 |sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 3 A -- MEM_SGMT 1 8 0 1 |sin_rom:u6|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\dds_vhdl\dds_vhdl.rpt
dds_vhdl
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 13/ 96( 13%) 20/ 48( 41%) 4/ 48( 8%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 4/ 48( 8%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
C: 9/ 96( 9%) 8/ 48( 16%) 3/ 48( 6%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 4/24( 16%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\dds_vhdl\dds_vhdl.rpt
dds_vhdl
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 32 clk
Device-Specific Information: e:\dds_vhdl\dds_vhdl.rpt
dds_vhdl
** EQUATIONS **
clk : INPUT;
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