dds_vhdl.hif

基于FPGA的直接数字频率合成器（DDS）设计 （源程序）

HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	reg8b.vhd
	{
		reg8b [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			22 [] [];
		}
	}
	adder8b.vhd
	{
		adder8b [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			21 [] [];
		}
	}
	altrom.tdf
	{
		altrom [DEVICE_FAMILY,REGISTERINPUTMODE=DEFAULT,FILE,NUMWORDS,AD_WIDTH,WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [memmodes.inc,lpm_decode.inc,lpm_mux.inc,aglobal.inc]
		{
			20 [DEVICE_FAMILY=FLEX10K,REGISTERINPUTMODE=ADDRESS_CONTROL,FILE="E:/DDS_VHDL/rom_data.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
			9 [DEVICE_FAMILY=FLEX10K,REGISTERINPUTMODE=ADDRESS_CONTROL,FILE="E:/Electronics/muxflie/DDS/rom_data.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
		}
	}
	lpm_rom.tdf
	{
		lpm_rom [DEVICE_FAMILY,LPM_FILE,LPM_OUTDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_NUMWORDS,LPM_WIDTHAD,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [altrom.inc,aglobal.inc]
		{
			19 [DEVICE_FAMILY=FLEX10K,LPM_FILE="E:/DDS_VHDL/rom_data.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [q0,q1,q2,q3,q4,q5,q6,q7,inclock,address0,address1,address2,address3,address4,address5,address6,address7];
			8 [DEVICE_FAMILY=FLEX10K,LPM_FILE="E:/Electronics/muxflie/DDS/rom_data.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [q0,q1,q2,q3,q4,q5,q6,q7,inclock,address0,address1,address2,address3,address4,address5,address6,address7];
		}
	}
	sin_rom.vhd
	{
		sin_rom [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			18 [] [];
		}
	}
	reg16b.vhd
	{
		reg16b [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			17 [] [];
		}
	}
	altshift.tdf
	{
		altshift [DEPTH=0,WIDTH=4,USE_LPM_FOR_AHDL_OPERATORS] []
		{
			13 [DEPTH=0,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result7,result6,result5,result4,result3,result2,result1,result0,data7,data6,data5,data4,data3,data2,data1,data0];
			5 [DEPTH=0,WIDTH=1,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result0,data0];
			4 [DEPTH=0,WIDTH=16,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result15,result14,result13,result12,result11,result10,result9,result8,result7,result6,result5,result4,result3,result2,result1,result0,data15,data14,data13,data12,data11,data10,data9,data8,data7,data6,data5,data4,data3,data2,data1,data0];
		}
	}
	addcore.tdf
	{
		addcore [DEVICE_FAMILY,CARRY_CHAIN_LENGTH,CARRY_CHAIN,CONSTANT_CIN,width,USE_LPM_FOR_AHDL_OPERATORS] [addcore.inc,aglobal.inc]
		{
			12 [DEVICE_FAMILY=FLEX10K,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,CONSTANT_CIN=0,width=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result7,result6,result5,result4,result3,result2,result1,result0,dataa7,dataa6,dataa5,dataa4,dataa3,dataa2,dataa1,dataa0,datab7,datab6,datab5,datab4,datab3,datab2,datab1,datab0,cin];
			3 [DEVICE_FAMILY=FLEX10K,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,CONSTANT_CIN=0,width=16,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result15,result14,result13,result12,result11,result10,result9,result8,result7,result6,result5,result4,result3,result2,result1,result0,dataa15,dataa14,dataa13,dataa12,dataa11,dataa10,dataa9,dataa8,dataa7,dataa6,dataa5,dataa4,dataa3,dataa2,dataa1,dataa0,datab15,datab14,datab13,datab12,datab11,datab10,datab9,datab8,datab7,datab6,datab5,datab4,datab3,datab2,datab1,datab0,cin];
		}
	}
	lpm_add_sub.tdf
	{
		lpm_add_sub [STYLE,DEVICE_FAMILY,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,OPTIMIZE_FOR_SPEED=5,MAXIMIZE_SPEED=5,LPM_PIPELINE=0,ONE_INPUT_IS_CONSTANT=NO,LPM_DIRECTION=DEFAULT,LPM_REPRESENTATION=SIGNED,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [lpm_add_sub.inc,addcore.inc,look_add.inc,bypassff.inc,altshift.inc,aglobal.inc]
		{
			11 [STYLE=NORMAL,DEVICE_FAMILY=FLEX10K,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,OPTIMIZE_FOR_SPEED=5,MAXIMIZE_SPEED=5,LPM_PIPELINE=0,ONE_INPUT_IS_CONSTANT=NO,LPM_DIRECTION=DEFAULT,LPM_REPRESENTATION=SIGNED,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [RESULT7,RESULT6,RESULT5,RESULT4,RESULT3,RESULT2,RESULT1,RESULT0,CIN,DATAB7,DATAB6,DATAB5,DATAB4,DATAB3,DATAB2,DATAB1,DATAB0,DATAA7,DATAA6,DATAA5,DATAA4,DATAA3,DATAA2,DATAA1,DATAA0];
			2 [STYLE=NORMAL,DEVICE_FAMILY=FLEX10K,CARRY_CHAIN_LENGTH=32,CARRY_CHAIN=IGNORE,OPTIMIZE_FOR_SPEED=5,MAXIMIZE_SPEED=5,LPM_PIPELINE=0,ONE_INPUT_IS_CONSTANT=NO,LPM_DIRECTION=DEFAULT,LPM_REPRESENTATION=SIGNED,LPM_WIDTH=16,USE_LPM_FOR_AHDL_OPERATORS=OFF] [RESULT15,RESULT14,RESULT13,RESULT12,RESULT11,RESULT10,RESULT9,RESULT8,RESULT7,RESULT6,RESULT5,RESULT4,RESULT3,RESULT2,RESULT1,RESULT0,CIN,DATAB15,DATAB14,DATAB13,DATAB12,DATAB11,DATAB10,DATAB9,DATAB8,DATAB7,DATAB6,DATAB5,DATAB4,DATAB3,DATAB2,DATAB1,DATAB0,DATAA15,DATAA14,DATAA13,DATAA12,DATAA11,DATAA10,DATAA9,DATAA8,DATAA7,DATAA6,DATAA5,DATAA4,DATAA3,DATAA2,DATAA1,DATAA0];
		}
	}
	adder16b.vhd
	{
		adder16b [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			16 [] [];
		}
	}
	dds_vhdl.vhd
	{
		dds_vhdl [] [U5125632.DLS,U9092257.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			0 [] [];
		}
	}
}
TREE
{
	dds_vhdl::(0,0):(0): dds_vhdl.vhd
	{
		adder16b:16:(46,7):(338,u1): adder16b.vhd
		{
			lpm_add_sub:2:(11,2):(49): lpm_add_sub.tdf
			{
				addcore:3:(212,4):(82,adder): addcore.tdf;
				altshift:4:(222,2):(137,result_ext_latency_ffs): altshift.tdf;
				altshift:5:(224,2):(175,carry_ext_latency_ffs): altshift.tdf;
				altshift:5:(226,2):(183,oflow_ext_latency_ffs): altshift.tdf;
			}
		}
		reg16b:17:(47,7):(339,u2): reg16b.vhd;
		sin_rom:18:(48,7):(340,u3): sin_rom.vhd
		{
			lpm_rom:19:(74,29):(50,lpm_rom_component): lpm_rom.tdf
			{
				altrom:20:(57,3):(46,srom): altrom.tdf;
			}
		}
		adder8b:21:(49,7):(341,u4): adder8b.vhd
		{
			lpm_add_sub:11:(11,2):(25): lpm_add_sub.tdf
			{
				addcore:12:(212,4):(58,adder): addcore.tdf;
				altshift:13:(222,2):(89,result_ext_latency_ffs): altshift.tdf;
				altshift:5:(224,2):(111,carry_ext_latency_ffs): altshift.tdf;
				altshift:5:(226,2):(119,oflow_ext_latency_ffs): altshift.tdf;
			}
		}
		reg8b:22:(50,7):(342,u5): reg8b.vhd;
		sin_rom:18:(51,7):(343,u6): sin_rom.vhd
		{
			lpm_rom:19:(74,29):(50,lpm_rom_component): lpm_rom.tdf
			{
				altrom:20:(57,3):(46,srom): altrom.tdf;
			}
		}
	}
}