📄 adder16b.rpt
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-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry8' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ008);
_EQ008 = b8 & _LC6_B23
# a8 & _LC6_B23
# a8 & b8;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry9' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = LCELL( _EQ009);
_EQ009 = b9 & _LC3_A4
# a9 & _LC3_A4
# a9 & b9;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry10' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ010);
_EQ010 = b10 & _LC4_A4
# a10 & _LC4_A4
# a10 & b10;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry11' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ011);
_EQ011 = b11 & _LC1_A4
# a11 & _LC1_A4
# a11 & b11;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry12' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ012);
_EQ012 = b12 & _LC4_A24
# a12 & _LC4_A24
# a12 & b12;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry13' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ013);
_EQ013 = b13 & _LC5_A24
# a13 & _LC5_A24
# a13 & b13;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|pcarry14' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ014);
_EQ014 = b14 & _LC6_A24
# a14 & _LC6_A24
# a14 & b14;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:161' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = LCELL( _EQ015);
_EQ015 = a0 & !b0
# !a0 & b0;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:178' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = LCELL( _EQ016);
_EQ016 = a0 & a1 & b0 & b1
# !a0 & a1 & !b1
# a1 & !b0 & !b1
# !a0 & !a1 & b1
# !a1 & !b0 & b1
# a0 & !a1 & b0 & !b1;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:179' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = LCELL( _EQ017);
_EQ017 = a2 & b2 & _LC4_C23
# !a2 & !b2 & _LC4_C23
# a2 & !b2 & !_LC4_C23
# !a2 & b2 & !_LC4_C23;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:180' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = LCELL( _EQ018);
_EQ018 = a3 & b3 & _LC6_C23
# !a3 & !b3 & _LC6_C23
# !a3 & b3 & !_LC6_C23
# a3 & !b3 & !_LC6_C23;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:181' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC8_B23', type is buried
_LC8_B23 = LCELL( _EQ019);
_EQ019 = a4 & b4 & _LC2_C23
# !a4 & !b4 & _LC2_C23
# !a4 & b4 & !_LC2_C23
# a4 & !b4 & !_LC2_C23;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:182' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = LCELL( _EQ020);
_EQ020 = a5 & b5 & _LC2_B23
# !a5 & !b5 & _LC2_B23
# !a5 & b5 & !_LC2_B23
# a5 & !b5 & !_LC2_B23;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:183' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = LCELL( _EQ021);
_EQ021 = a6 & b6 & _LC4_B23
# !a6 & !b6 & _LC4_B23
# !a6 & b6 & !_LC4_B23
# a6 & !b6 & !_LC4_B23;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:184' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_B23', type is buried
_LC5_B23 = LCELL( _EQ022);
_EQ022 = a7 & b7 & _LC7_B23
# !a7 & !b7 & _LC7_B23
# !a7 & b7 & !_LC7_B23
# a7 & !b7 & !_LC7_B23;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:185' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = LCELL( _EQ023);
_EQ023 = a8 & b8 & _LC6_B23
# !a8 & !b8 & _LC6_B23
# !a8 & b8 & !_LC6_B23
# a8 & !b8 & !_LC6_B23;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:186' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ024);
_EQ024 = a9 & b9 & _LC3_A4
# !a9 & !b9 & _LC3_A4
# !a9 & b9 & !_LC3_A4
# a9 & !b9 & !_LC3_A4;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:187' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = LCELL( _EQ025);
_EQ025 = a10 & b10 & _LC4_A4
# !a10 & !b10 & _LC4_A4
# !a10 & b10 & !_LC4_A4
# a10 & !b10 & !_LC4_A4;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:188' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ026);
_EQ026 = a11 & b11 & _LC1_A4
# !a11 & !b11 & _LC1_A4
# !a11 & b11 & !_LC1_A4
# a11 & !b11 & !_LC1_A4;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:189' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ027);
_EQ027 = a12 & b12 & _LC4_A24
# !a12 & !b12 & _LC4_A24
# !a12 & b12 & !_LC4_A24
# a12 & !b12 & !_LC4_A24;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:190' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ028);
_EQ028 = a13 & b13 & _LC5_A24
# !a13 & !b13 & _LC5_A24
# !a13 & b13 & !_LC5_A24
# a13 & !b13 & !_LC5_A24;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:191' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC8_A24', type is buried
_LC8_A24 = LCELL( _EQ029);
_EQ029 = a14 & b14 & _LC6_A24
# !a14 & !b14 & _LC6_A24
# !a14 & b14 & !_LC6_A24
# a14 & !b14 & !_LC6_A24;
-- Node name is '|LPM_ADD_SUB:49|addcore:adder|:192' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_C17', type is buried
_LC4_C17 = LCELL( _EQ030);
_EQ030 = a15 & b15 & _LC1_A24
# !a15 & !b15 & _LC1_A24
# !a15 & b15 & !_LC1_A24
# a15 & !b15 & !_LC1_A24;
Project Information e:\electronics\muxflie\dds_vhdl\adder16b.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,558K
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