lib.dls

基于FPGA的直接数字频率合成器（DDS）设计 （源程序）

DLSL
1
ADDER16B.VHDLVIEW U1319630.DLS
ADDER16B-BEHAV.SYNTHESISVIEW U8571616.DLS
ADDER16B-BEHAV.VHDLVIEW U9420835.DLS
ADDER8B.VHDLVIEW U2510018.DLS
ADDER8B-BEHAV.SYNTHESISVIEW U4544140.DLS
ADDER8B-BEHAV.VHDLVIEW U9243931.DLS
DDS_VHDL.VHDLVIEW U4254068.DLS
DDS_VHDL-ONE.SYNTHESISVIEW U6981785.DLS
DDS_VHDL-ONE.VHDLVIEW U2982244.DLS
REG16B.VHDLVIEW U7046678.DLS
REG16B-BEHAV.SYNTHESISVIEW U5966069.DLS
REG16B-BEHAV.VHDLVIEW U7161597.DLS
REG8B.VHDLVIEW U4037617.DLS
REG8B-BEHAV.SYNTHESISVIEW U3383096.DLS
REG8B-BEHAV.VHDLVIEW U1156317.DLS
SIN_ROM.VHDLVIEW U8363834.DLS
SIN_ROM-SYN.SYNTHESISVIEW U1588124.DLS
SIN_ROM-SYN.VHDLVIEW U2707218.DLS