pt.vhd

FPGA display red,blue and green color

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pt is
port(
     
     clk_in:in std_logic;
     v_in:in std_logic;
     h_in:in std_logic;
     clk_out:out std_logic;
     h:out std_logic:='0';
     v:out std_logic:='0';
     en:out std_logic:='0';
     qout:out std_logic:='0';
     rd:out std_logic_vector(7 downto 0):=(others=>'0');
     gd:out std_logic_vector(7 downto 0):=(others=>'1');
     bd:out std_logic_vector(7 downto 0):=(others=>'0')
    );
end;

architecture pt_architecture of pt is

begin


hv_clock:process(clk_in)
         variable cnt_h:integer:=0;      --行计数（单位：时钟次数）  
         variable cnt_v:integer:=0;      --场计数
         variable cnt_c:integer:=0;
         variable T0:  integer:= 128;    --数据转换时间
         variable T1:  integer := 216;   --行与数据使能对齐
         variable T2:  integer := 1016;  --数据使能
         variable T3:  integer := 1188;  --行场对齐
         variable T4:  integer := 1188;  --行扫描
         variable T5:  integer := 3;     --场消隐
         variable T6:  integer := 628;   --场扫描  

    begin
     
      clk_out<=clk_in;
      if rising_edge(clk_in) then
         cnt_h:=cnt_h+1;

            if cnt_h>T0 then

------------------------------------------ enable signal
                --if cnt_h>T1 then

                   --if cnt_h<T2 then
                       --en<='1';
                    --else
                       --en<='0';
                   --end if;
                   --else
                      --en<='0';
                  --end if;
------------------------------------------v signal
               if cnt_h=T4 then
                  cnt_v:=cnt_v+1;
                 if cnt_v>T5 then
                    if cnt_v<T6 then
                     v<='1';
                     else 
                      cnt_v:=0;
                       v<='0';
--------------------------------------------
cnt_c:=cnt_c+1;
 if cnt_c<1000 then 
     rd<=(others=>'0');
     gd<=(others=>'1');
     bd<=(others=>'0');
    else if cnt_c<2000 then
          rd<=(others=>'1');
          gd<=(others=>'0');
          bd<=(others=>'0');
             else if cnt_c<3000 then
                       rd<=(others=>'0');
                       gd<=(others=>'0');
                       bd<=(others=>'1');
                       else
                       cnt_c:=0;
                   end if;
           end if;
    end if; 


--------------------------------------------

                    end if;
                  else 
                    v<='0';
                  end if;
               end if;             
--------------------------------------------
               if cnt_h<T3 then
                  h<='1';
                else
                  cnt_h:=0;
                  h<='0';
               end if;
            else
                h<='0';
            end if;
     end if;

    end process;



 pwm:process(clk_in)                        
    variable cnt:integer:=0;
    begin
        if rising_edge(clk_in) then
          cnt:=cnt+1;
            if cnt>200 then              
                 if cnt<235 then
                    qout<='1';
                     else
                      cnt:=0;
                      qout<='0';
                 end if;
            else
                qout<='0';
            end if;
       end if;
     end process;



end pt_architecture;