prev_cmp_fpga_uartrw.qmsg

FPGA的uart控制器的verilog源程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 07 10:00:44 2008 " "Info: Processing started: Wed May 07 10:00:44 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fpga_uartrw -c fpga_uartrw " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fpga_uartrw -c fpga_uartrw" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fpga_receiver.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fpga_receiver.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_receiver " "Info: Found entity 1: uart_receiver" {  } { { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fpga_transmitter.v(27) " "Warning (10268): Verilog HDL information at fpga_transmitter.v(27): Always Construct contains both blocking and non-blocking assignments" {  } { { "fpga_transmitter.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_transmitter.v" 27 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fpga_transmitter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fpga_transmitter.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_transmitter " "Info: Found entity 1: uart_transmitter" {  } { { "fpga_transmitter.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_transmitter.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fpga_uartrw.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file fpga_uartrw.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 fpga_uartrw " "Info: Found entity 1: fpga_uartrw" {  } { { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fpga_uartrw " "Info: Elaborating entity \"fpga_uartrw\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_transmitter uart_transmitter:inst " "Info: Elaborating entity \"uart_transmitter\" for hierarchy \"uart_transmitter:inst\"" {  } { { "fpga_uartrw.bdf" "inst" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 96 376 552 192 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 17 fpga_transmitter.v(21) " "Warning (10230): Verilog HDL assignment warning at fpga_transmitter.v(21): truncated value with size 32 to match size of target (17)" {  } { { "fpga_transmitter.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_transmitter.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_receiver uart_receiver:inst1 " "Info: Elaborating entity \"uart_receiver\" for hierarchy \"uart_receiver:inst1\"" {  } { { "fpga_uartrw.bdf" "inst1" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 112 160 320 208 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RxD_data_error fpga_receiver.v(132) " "Warning (10036): Verilog HDL or VHDL warning at fpga_receiver.v(132): object \"RxD_data_error\" assigned a value but never read" {  } { { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 132 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 17 fpga_receiver.v(21) " "Warning (10230): Verilog HDL assignment warning at fpga_receiver.v(21): truncated value with size 32 to match size of target (17)" {  } { { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "uart_receiver:inst1\|Baud8GeneratorAcc\[1\] uart_receiver:inst1\|Baud8GeneratorAcc\[0\] " "Info: Duplicate register \"uart_receiver:inst1\|Baud8GeneratorAcc\[1\]\" merged to single register \"uart_receiver:inst1\|Baud8GeneratorAcc\[0\]\"" {  } { { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 24 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "uart_receiver:inst1\|Baud8GeneratorAcc\[2\] uart_receiver:inst1\|Baud8GeneratorAcc\[0\] " "Info: Duplicate register \"uart_receiver:inst1\|Baud8GeneratorAcc\[2\]\" merged to single register \"uart_receiver:inst1\|Baud8GeneratorAcc\[0\]\"" {  } { { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 24 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}