fpga_uartrw.tan.rpt

FPGA的uart控制器的verilog源程序

; Device Name                                           ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                      ; To                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 234.91 MHz ( period = 4.257 ns )                    ; uart_receiver:inst1|bit_spacing[0]        ; uart_receiver:inst1|RxD_data[6]            ; clk        ; clk      ; None                        ; None                      ; 4.018 ns                ;
; N/A                                     ; 234.91 MHz ( period = 4.257 ns )                    ; uart_receiver:inst1|bit_spacing[0]        ; uart_receiver:inst1|RxD_data[7]            ; clk        ; clk      ; None                        ; None                      ; 4.018 ns                ;
; N/A                                     ; 234.91 MHz ( period = 4.257 ns )                    ; uart_receiver:inst1|bit_spacing[0]        ; uart_receiver:inst1|RxD_data[2]            ; clk        ; clk      ; None                        ; None                      ; 4.018 ns                ;
; N/A                                     ; 234.91 MHz ( period = 4.257 ns )                    ; uart_receiver:inst1|bit_spacing[0]        ; uart_receiver:inst1|RxD_data[3]            ; clk        ; clk      ; None                        ; None                      ; 4.018 ns                ;
; N/A                                     ; 234.91 MHz ( period = 4.257 ns )                    ; uart_receiver:inst1|bit_spacing[0]        ; uart_receiver:inst1|RxD_data[5]            ; clk        ; clk      ; None                        ; None                      ; 4.018 ns                ;
; N/A                                     ; 234.91 MHz ( period = 4.257 ns )                    ; uart_receiver:inst1|bit_spacing[0]        ; uart_receiver:inst1|RxD_data[0]            ; clk        ; clk      ; None                        ; None                      ; 4.018 ns                ;
; N/A                                     ; 234.91 MHz ( period = 4.257 ns )                    ; uart_receiver:inst1|bit_spacing[0]        ; uart_receiver:inst1|RxD_data[4]            ; clk        ; clk      ; None                        ; None                      ; 4.018 ns                ;
; N/A                                     ; 234.91 MHz ( period = 4.257 ns )                    ; uart_receiver:inst1|bit_spacing[0]        ; uart_receiver:inst1|RxD_data[1]            ; clk        ; clk      ; None                        ; None                      ; 4.018 ns                ;
; N/A                                     ; 243.37 MHz ( period = 4.109 ns )                    ; uart_receiver:inst1|bit_spacing[3]        ; uart_receiver:inst1|RxD_data[6]            ; clk        ; clk      ; None                        ; None                      ; 3.870 ns                ;
; N/A                                     ; 243.37 MHz ( period = 4.109 ns )                    ; uart_receiver:inst1|bit_spacing[3]        ; uart_receiver:inst1|RxD_data[7]            ; clk        ; clk      ; None                        ; None                      ; 3.870 ns                ;
; N/A                                     ; 243.37 MHz ( period = 4.109 ns )                    ; uart_receiver:inst1|bit_spacing[3]        ; uart_receiver:inst1|RxD_data[2]            ; clk        ; clk      ; None                        ; None                      ; 3.870 ns                ;
; N/A                                     ; 243.37 MHz ( period = 4.109 ns )                    ; uart_receiver:inst1|bit_spacing[3]        ; uart_receiver:inst1|RxD_data[3]            ; clk        ; clk      ; None                        ; None                      ; 3.870 ns                ;
; N/A                                     ; 243.37 MHz ( period = 4.109 ns )                    ; uart_receiver:inst1|bit_spacing[3]        ; uart_receiver:inst1|RxD_data[5]            ; clk        ; clk      ; None                        ; None                      ; 3.870 ns                ;
; N/A                                     ; 243.37 MHz ( period = 4.109 ns )                    ; uart_receiver:inst1|bit_spacing[3]        ; uart_receiver:inst1|RxD_data[0]            ; clk        ; clk      ; None                        ; None                      ; 3.870 ns                ;
; N/A                                     ; 243.37 MHz ( period = 4.109 ns )                    ; uart_receiver:inst1|bit_spacing[3]        ; uart_receiver:inst1|RxD_data[4]            ; clk        ; clk      ; None                        ; None                      ; 3.870 ns                ;
; N/A                                     ; 243.37 MHz ( period = 4.109 ns )                    ; uart_receiver:inst1|bit_spacing[3]        ; uart_receiver:inst1|RxD_data[1]            ; clk        ; clk      ; None                        ; None                      ; 3.870 ns                ;
; N/A                                     ; 249.88 MHz ( period = 4.002 ns )                    ; uart_receiver:inst1|bit_spacing[1]        ; uart_receiver:inst1|RxD_data[6]            ; clk        ; clk      ; None                        ; None                      ; 3.763 ns                ;
; N/A                                     ; 249.88 MHz ( period = 4.002 ns )                    ; uart_receiver:inst1|bit_spacing[1]        ; uart_receiver:inst1|RxD_data[7]            ; clk        ; clk      ; None                        ; None                      ; 3.763 ns                ;
; N/A                                     ; 249.88 MHz ( period = 4.002 ns )                    ; uart_receiver:inst1|bit_spacing[1]        ; uart_receiver:inst1|RxD_data[2]            ; clk        ; clk      ; None                        ; None                      ; 3.763 ns                ;
; N/A                                     ; 249.88 MHz ( period = 4.002 ns )                    ; uart_receiver:inst1|bit_spacing[1]        ; uart_receiver:inst1|RxD_data[3]            ; clk        ; clk      ; None                        ; None                      ; 3.763 ns                ;
; N/A                                     ; 249.88 MHz ( period = 4.002 ns )                    ; uart_receiver:inst1|bit_spacing[1]        ; uart_receiver:inst1|RxD_data[5]            ; clk        ; clk      ; None                        ; None                      ; 3.763 ns                ;
; N/A                                     ; 249.88 MHz ( period = 4.002 ns )                    ; uart_receiver:inst1|bit_spacing[1]        ; uart_receiver:inst1|RxD_data[0]            ; clk        ; clk      ; None                        ; None                      ; 3.763 ns                ;
; N/A                                     ; 249.88 MHz ( period = 4.002 ns )                    ; uart_receiver:inst1|bit_spacing[1]        ; uart_receiver:inst1|RxD_data[4]            ; clk        ; clk      ; None                        ; None                      ; 3.763 ns                ;