cmultipler.fit.smsg

复乘法器的FPGA实现

    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Automatically promoted node reset (placed in PIN M21 (CLK1p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 129 (unused VREF, 3.30 VCCIO, 65 input, 64 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  39 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  43 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  49 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  35 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  44 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  40 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  34 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 3.744 ns
    Info: 1: + IC(0.000 ns) + CELL(0.190 ns) = 0.190 ns; Loc. = DSPMULT_X28_Y4_N0; Fanout = 1; REG Node = 'MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|mac_mult2~DATAOUT15'
    Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 0.790 ns; Loc. = DSPOUT_X28_Y4_N2; Fanout = 4; COMB Node = 'MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[15]'
    Info: 3: + IC(0.601 ns) + CELL(0.545 ns) = 1.936 ns; Loc. = LAB_X29_Y3; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[0]~COUT'
    Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 1.971 ns; Loc. = LAB_X29_Y3; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[1]~COUT'
    Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 2.006 ns; Loc. = LAB_X29_Y3; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[2]~COUT'
    Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 2.041 ns; Loc. = LAB_X29_Y3; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[3]~COUT'
    Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 2.076 ns; Loc. = LAB_X29_Y3; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[4]~COUT'
    Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 2.111 ns; Loc. = LAB_X29_Y3; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[5]~COUT'
    Info: 9: + IC(0.000 ns) + CELL(0.035 ns) = 2.146 ns; Loc. = LAB_X29_Y3; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[6]~COUT'
    Info: 10: + IC(0.000 ns) + CELL(0.035 ns) = 2.181 ns; Loc. = LAB_X29_Y3; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[7]~COUT'
    Info: 11: + IC(0.132 ns) + CELL(0.035 ns) = 2.348 ns; Loc. = LAB_X29_Y2; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[8]~COUT'
    Info: 12: + IC(0.000 ns) + CELL(0.035 ns) = 2.383 ns; Loc. = LAB_X29_Y2; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[9]~COUT'
    Info: 13: + IC(0.000 ns) + CELL(0.035 ns) = 2.418 ns; Loc. = LAB_X29_Y2; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[10]~COUT'
    Info: 14: + IC(0.000 ns) + CELL(0.035 ns) = 2.453 ns; Loc. = LAB_X29_Y2; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[11]~COUT'
    Info: 15: + IC(0.000 ns) + CELL(0.035 ns) = 2.488 ns; Loc. = LAB_X29_Y2; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[12]~COUT'
    Info: 16: + IC(0.000 ns) + CELL(0.035 ns) = 2.523 ns; Loc. = LAB_X29_Y2; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[13]~COUT'
    Info: 17: + IC(0.000 ns) + CELL(0.035 ns) = 2.558 ns; Loc. = LAB_X29_Y2; Fanout = 2; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[14]~COUT'
    Info: 18: + IC(0.000 ns) + CELL(0.035 ns) = 2.593 ns; Loc. = LAB_X29_Y2; Fanout = 1; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[15]~COUT'
    Info: 19: + IC(0.088 ns) + CELL(0.125 ns) = 2.806 ns; Loc. = LAB_X29_Y2; Fanout = 16; COMB Node = 'ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[16]'
    Info: 20: + IC(0.511 ns) + CELL(0.272 ns) = 3.589 ns; Loc. = LAB_X29_Y3; Fanout = 1; COMB Node = 'ADDSUB_16_0:add3|result[0]~731'
    Info: 21: + IC(0.000 ns) + CELL(0.155 ns) = 3.744 ns; Loc. = LAB_X29_Y3; Fanout = 1; REG Node = 'sigbuf5[0]'
    Info: Total cell delay = 2.412 ns ( 64.42 % )
    Info: Total interconnect delay = 1.332 ns ( 35.58 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 3%
    Info: The peak interconnect region extends from location X27_Y0 to location X40_Y13
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 64 output pins without output pin load capacitance assignment
    Info: Pin "iout[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "iout[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qout[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "tempout[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Following 16 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin tempout[16] has GND driving its datain port
    Info: Pin tempout[17] has GND driving its datain port
    Info: Pin tempout[18] has GND driving its datain port
    Info: Pin tempout[19] has GND driving its datain port
    Info: Pin tempout[20] has GND driving its datain port
    Info: Pin tempout[21] has GND driving its datain port
    Info: Pin tempout[22] has GND driving its datain port
    Info: Pin tempout[23] has GND driving its datain port
    Info: Pin tempout[24] has GND driving its datain port
    Info: Pin tempout[25] has GND driving its datain port
    Info: Pin tempout[26] has GND driving its datain port
    Info: Pin tempout[27] has GND driving its datain port
    Info: Pin tempout[28] has GND driving its datain port
    Info: Pin tempout[29] has GND driving its datain port
    Info: Pin tempout[30] has GND driving its datain port
    Info: Pin tempout[31] has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
    Info: Allocated 204 megabytes of memory during processing
    Info: Processing ended: Tue May 06 14:11:11 2008
    Info: Elapsed time: 00:00:14