gendc.vhd

对ARM核的VHDL描述

-- $(help_generic)
-- $(help_local)

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.conv_integer;
use IEEE.std_logic_arith.conv_unsigned;
use work.config.all;
use work.int.all;
use work.memdef.all;
use work.corelib.all;
use work.cache_comp.all;
use work.cache_config.all;
use work.genic_lib.all;
use work.gendc_lib.all;
use work.genwb_lib.all;
use work.gencmem_lib.all;
use work.setrepl_lib.all;
use work.arith_cnt_comp.all;
use work.bus_comp.all;

entity gendc is
  port ( 
    rst     : in  std_logic; 
    clk     : in  std_logic;
    hold : in cli_hold;
    i  : in  gendc_type_in;
    o  : out gendc_type_out;
    ctrl : in gdcl_ctrl;
    dcmo : in gencmem_type_dc_out;
    dcmi : out gencmem_type_dc_in;
    wbi  : out genwb_type_in;
    wbo  : in genwb_type_out
    );
end gendc;

architecture rtl of gendc is
  
  type gendc_dirty_a is array (natural range <>) of std_logic_vector(GCML_DC_TADDR_BSZ-1 downto 0);
  
  type gendc_cmaddrsrc is (gdca_no, gdca_in,  gdca_re,  gdca_lo);
  type gendc_meaddrsrc is (gdcma_no, gdcma_in, gdcma_re, gdcma_lo );
  type gendc_datainsrc is (gdcdi_no, gdcdi_in, gdcdi_re, gdcdi_lo, gdcdi_me );
  type gendc_datapisrc is (gdcdp_cm, gdcdp_me, gdcdp_no );
  type gendc_dbsrc is (gdcdb_mem, gdcdb_cm );
  
  type gendc_validsrc is (gdcvalid_old, gdcvalid_clr, gdcvalid_new, gdcvalid_add );
  type gendc_dirtysrc is (gdcdirty_old, gdcdirty_clr, gdcdirty_new, gdcdirty_add );

  constant GCML_DC_DLINE_BSZ_X : integer := lin_log2x(CFG_DC_DLINE_SZ); 
  constant GCML_DC_SETS_X  : integer := lin_log2x(CFG_DC_SETS); 

  type gendc_tmp_type is record
    hit, valid, dirty  : std_logic;     -- cache line attr 
    set, setrep  : integer;                     -- hit set
    pos  : integer;                     -- line pos
    ehold, req, reqread, reqwrite : std_logic;
    sethit  : std_logic_vector(CFG_DC_SETS-1 downto 0);
    setvalid   : std_logic_vector(CFG_DC_SETS-1 downto 0);
    newvalid, newdirty : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0);
    twrite, dwrite : std_logic;
    mexc : std_logic;
    
    setpos : std_logic_vector(lin_log2x(CFG_DC_SETS)-1 downto 0);
    
    cmaddr : std_logic_vector(31 downto 0);
    datain : std_logic_vector(31 downto 0);
    meaddr : std_logic_vector(31 downto 0);
    datapi : std_logic_vector(31 downto 0);
    tvalid_src : gendc_validsrc;
    tdirty_src : gendc_dirtysrc;
    cmaddr_src : gendc_cmaddrsrc;
    datain_src : gendc_datainsrc;
    meaddr_src : gendc_meaddrsrc;
    datapi_src : gendc_datapisrc;
    db_src : gendc_dbsrc;
    
    sign, read, lock, burst : std_logic;
    size : lmd_memsize;       
    linepos : std_logic_vector(GCML_DC_TLINE_BSZ-1 downto 0);
    linepos_lastbit : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0);
    
    cmset : integer;
    
    si : arith_cnt8_in;
    dcmi : gencmem_type_dc_in;
    wbi  : genwb_type_in;
    o  : gendc_type_out;
    
    sr_setfree : std_logic_vector(CFG_DC_SETS-1 downto 0);
    sr_setlock : std_logic_vector(CFG_DC_SETS-1 downto 0);
    sr_useset : std_logic;
  end record;
  type gendc_state is (gendc_hit, 
                       gendc_wtwb_readdata,
                       gendc_wb_writedata, gendc_wt_writedata,
                       gendc_wb_wbline, gendc_wb_fillline, 
                       gendc_reloadtaddr );
  type gendc_reg_type is record
    setrep : std_logic_vector(lin_log2x(CFG_DC_SETS)-1 downto 0);
    state, state_wbline_next : gendc_state;
    hit, hold : std_logic;

    p_address : std_logic_vector(31 downto 0);
    p_data : std_logic_vector(31 downto 0);
    p_sign, p_read, p_lock : std_logic;
    p_size : lmd_memsize; 
    
    stored, wbready, wbnext : std_logic;
    setrep_locked, setrep_free : std_logic;
    o_wr_data : std_logic_vector(31 downto 0);
    addrlo : std_logic_vector(1 downto 0);
    dirty : std_logic_vector(CFG_DC_TLINE_SZ-1 downto 0);
    fill_linepos, linepos : std_logic_vector(GCML_DC_TLINE_BSZ-1 downto 0);
    doaddr : std_logic_vector(1 downto 0);
    mexc : std_logic;
  end record;
  type gendc_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     cmaddr : std_logic_vector(31 downto 0);
     dbg : gendc_tmp_type;
     -- pragma translate_on
  end record;
  signal r, c       : gendc_reg_type;
  signal rdbg, cdbg : gendc_dbg_type;

  signal si : arith_cnt8_in;
  signal so : arith_cnt8_out;
  
  signal sr_setfree : std_logic_vector(CFG_DC_SETS-1 downto 0);
  signal sr_setlock : std_logic_vector(CFG_DC_SETS-1 downto 0);
  signal sr_useset : std_logic;
  signal sr_locked : std_logic;
  signal sr_free   : std_logic;
  signal sr_setrep_free : std_logic_vector(GCML_DC_SETS_X-1 downto 0);
  signal sr_setrep_repl : std_logic_vector(GCML_DC_SETS_X-1 downto 0);
    
begin  
    
  p0: process (clk, rst, r, hold, i, dcmo, wbo, so,
               sr_locked, sr_free, sr_setrep_free, sr_setrep_repl )
    variable v    : gendc_reg_type;
    variable t    : gendc_tmp_type;
    variable vdbg : gendc_dbg_type;
  begin
    
    -- todo: locking on atomic load store does not work yet
    -- until no multiprocessor system is implemented it's defered to the future
    
    -- $(init(t:gendc_tmp_type))
    v := r;
    
    t.meaddr := i.addr_in;
    t.cmaddr := i.addr_in;
    t.datain := i.data_in;
    
    t.wbi.fifo_write := '0';
    v.stored := r.stored or wbo.fifo_stored_v;
    
    -- write back address
    t.si.data := (others => '0');
    t.si.data(arith_cnt8_SZ-1 downto arith_cnt8_SZ-CFG_DC_TLINE_SZ) := r.dirty;
    t.linepos := so.res(GCML_DC_TLINE_BSZ-1 downto 0);
    t.linepos_lastbit := (others => '0');

    t.mexc := '0';
    
    t.datapi_src := gdcdp_no;
    t.db_src := gdcdb_cm;
    
    t.ehold := hold.ihold;
    t.req := (not (t.ehold or i.annul)) and i.addrin_re ;
    t.reqread := i.param_r.read and t.req;
    t.reqwrite := (not i.param_r.read) and t.req;
    t.twrite := '0';
    t.dwrite := '0';
    
    if r.hit = '1' then
      t.tvalid_src := gdcvalid_add;
      t.tdirty_src := gdcdirty_add;
    else
      t.tvalid_src := gdcvalid_new;
      t.tdirty_src := gdcdirty_new;
    end if;

    t.burst := '0';
    if (r.hold or t.ehold) = '1' then
      t.cmaddr_src := gdca_re;
      t.meaddr_src := gdcma_lo;
      t.datain_src := gdcdi_lo;
      t.sign := r.p_sign;
      t.size := r.p_size;
      t.read := r.p_read;
      t.lock := r.p_lock;
    else
      t.cmaddr_src := gdca_in;
      t.meaddr_src := gdcma_re;
      t.datain_src := gdcdi_in;
      t.sign := i.param_r.signed;
      t.size := i.param_r.size;
      t.read := i.param_r.read;
      t.lock := i.param_r.lock;
    end if;
    
    if t.read = '1' then
      t.size := lmd_word;
    end if;
        
    -- cmp
    t.hit := '0';
    t.set := 0;
    for j in CFG_DC_SETS-1 downto 0 loop
      -- (note: multiset does not recognice valid zero tags)
      if gdcl_is_taghit(i.addr_re,dcmo.tag_line(j)) then
        t.hit := '1';
        t.sethit(j) := '1';
        t.set := j;
      end if;
    end loop; 
        
    t.sr_setfree := (others => '0');
    for j in CFG_DC_SETS-1 downto 0 loop
      if gdcl_is_free(dcmo.tag_line(j)) then
        t.sr_setfree(j) := '1';
      end if;
    end loop; 
    
    t.sr_setlock := (others => '0');
    for j in CFG_DC_SETS-1 downto 0 loop
      t.sr_setlock(j) := dcmo.tag_line(j).lock;
    end loop; 

    t.sr_useset := '0';
    
    t.valid := '0';
    if gdcl_is_linevalid(i.addr_re,dcmo.tag_line(t.set)) then
      t.valid := '1';
    end if;

    t.dirty := '0';
    t.setrep := lin_convint(sr_setrep_repl);
    if (sr_free = '1') or (sr_locked = '1') then
      t.dirty := '0';
      if (sr_free = '1') then
        t.setrep := lin_convint(sr_setrep_free);
      end if;
    else
      if gdcl_is_linedirty(i.addr_re,dcmo.tag_line(t.setrep)) then
        t.dirty := '1';
      end if;
    end if;
      
    -- $(del)
    --                read                               write                                                
    --   Writeback     |   Writethrough     Writeback     |   Writethrough                                        
    --        +--------+--------+                +--------+--------+                                                  
    --    hit | miss        hit | miss       hit | miss        hit | miss                                      
    --   +----+----+       +----+----+      +----+----+       +----+----+                               
    --   |     free|dirty  |         |      |     free|dirty  |         |                   
    --   O1     +--+--+    O1        O3    O5      +--+--+   O4/O6     O6                              
    --          |     |              |             |     |                                            
    --          O3<---O2             O4            O5<---O2                                            
    --          |                                                                                                     
    --          O4                                                                                     
    --                                                                                                        
    --  O1: cacheread                                                                                                  
    --  O2: writeback line                                                                                              
    --  O3: memload                                                                                                     
    --  O4: cachewrite clean                                                                                              
    --  O5: cachewrite dirty                                                                                             
    --  O6: writeback single                                                                                            
    -- $(/del)

        
    case r.state is
      
      when gendc_hit =>

        if t.hit = '1' then
          t.tvalid_src := gdcvalid_add;
          t.tdirty_src := gdcdirty_add;
        else
          t.tvalid_src := gdcvalid_new;
          t.tdirty_src := gdcdirty_new;
        end if;

        v.mexc := '0';
        v.wbready := '0';
        v.wbnext := '0';
        v.stored := wbo.fifo_stored_v;
        v.hold := '0';
        
        v.setrep_locked := sr_locked;
        v.setrep_free := sr_free;
        
        v.hit := t.hit;
        
        v.p_address := i.addr_re;
        v.p_data := i.data_in;
        v.p_sign := i.param_r.signed;
        v.p_size := i.param_r.size;
        v.p_read := i.param_r.read;
        v.p_lock := i.param_r.lock;
  
        if t.req = '1' then
          
          t.sr_useset := '1';
    
          if i.param_r.read = '1' then
            if ctrl.writeback = '0' then
              if (not (t.hit and t.valid)) = '1' or (i.forceread = '1') then
                
                -- $(del)
                --                read               
                --   Writeback     |   Writethrough  
                --        +--------+--------+        
                --    hit | miss        hit |<MISS>                   
                --   +----+----+       +----+----+   
                --   |     free|dirty  |         |   
                --   O1     +--+--+    O1        O3  
                --          |     |              |   
                --          O3<---O2             O4  
                --          |                        
                --          O4
                -- $(/del)
                
                -- $(del)
                -- $(/del)
                t.cmaddr_src := gdca_re;

                v.hold := '1';
                
                t.wbi.fifo_write := '1';
                v.state := gendc_wtwb_readdata;
                
              else                                                          
                
                -- $(del)
                --                read               
                --   Writeback     |   Writethrough  
                --        +--------+--------+        
                --    hit | miss       <HIT>| miss                   
                --   +----+----+       +----+----+   
                --   |     free|dirty  |         |