dds_top.map.eqn

实现数字频率合成。能产生任意频率的正弦信号、方波信号、梯形波等

--AB9_16 is cepin:inst9|74175:inst6|16
--operation mode is normal

AB9_16_lut_out = HB2_6;
AB9_16 = DFFEAS(AB9_16_lut_out, !inst13, cl, , , , , , );


--AB8_16 is cepin:inst9|74175:inst5|16
--operation mode is normal

AB8_16_lut_out = HB1_6;
AB8_16 = DFFEAS(AB8_16_lut_out, !inst13, cl, , , , , , );


--R1L1 is 74157:inst22|22~40
--operation mode is normal

R1L1 = HB21_7 & (HB21_6) # !HB21_7 & (HB21_6 & AB9_16 # !HB21_6 & (AB8_16));


--AB11_16 is cepin:inst9|74175:inst8|16
--operation mode is normal

AB11_16_lut_out = HB4_6;
AB11_16 = DFFEAS(AB11_16_lut_out, !inst13, cl, , , , , , );


--R1L2 is 74157:inst22|22~41
--operation mode is normal

R1L2 = HB21_7 & (R1L1 & (AB11_16) # !R1L1 & AB01_16) # !HB21_7 & (R1L1);


--HB11_6 is kuopx:inst19|74160:inst4|6
--operation mode is normal

HB11_6_lut_out = !K2_inst5 & (HB11_6 $ (HB01_9 & HB11L6));
HB11_6 = DFFEAS(HB11_6_lut_out, cpp0, cl, , , , , , );


--HB01_6 is kuopx:inst19|74160:inst1|6
--operation mode is normal

HB01_6_lut_out = HB9_8 & !K2L2 & (HB01_6 $ HB11L7) # !HB9_8 & (HB01_6 $ HB11L7);
HB01_6 = DFFEAS(HB01_6_lut_out, cpp0, cl, , , , , , );


--KB5L1 is 24x4:inst18|74151:inst|f74151:sub|73~56
--operation mode is normal

KB5L1 = !HB21_7 & (HB21_6 & HB11_6 # !HB21_6 & (HB01_6));


--HB7_6 is kuopx:inst14|74160:inst1|6
--operation mode is normal

HB7_6_lut_out = HB6_8 & !K1L2 & (HB7_6 $ HB8L7) # !HB6_8 & (HB7_6 $ HB8L7);
HB7_6 = DFFEAS(HB7_6_lut_out, cpx0, cl, , , , , , );


--HB8_6 is kuopx:inst14|74160:inst4|6
--operation mode is normal

HB8_6_lut_out = !K1_inst5 & (HB8_6 $ (HB7_9 & HB8L6));
HB8_6 = DFFEAS(HB8_6_lut_out, cpx0, cl, , , , , , );


--HB6_6 is kuopx:inst14|74160:inst|6
--operation mode is normal

HB6_6_lut_out = HB6_8 & !K1L2 & (HB6_6 $ DB31L5) # !HB6_8 & (HB6_6 $ DB31L5);
HB6_6 = DFFEAS(HB6_6_lut_out, cpx0, cl, , , , , , );


--R1L3 is 74157:inst22|22~42
--operation mode is normal

R1L3 = HB21_6 & (HB21_7) # !HB21_6 & (HB21_7 & HB8_6 # !HB21_7 & (HB6_6));


--HB9_6 is kuopx:inst19|74160:inst|6
--operation mode is normal

HB9_6_lut_out = HB9_8 & !K2L2 & (HB9_6 $ DB31L5) # !HB9_8 & (HB9_6 $ DB31L5);
HB9_6 = DFFEAS(HB9_6_lut_out, cpp0, cl, , , , , , );


--R1L4 is 74157:inst22|22~43
--operation mode is normal

R1L4 = HB21_6 & (R1L3 & (HB9_6) # !R1L3 & HB7_6) # !HB21_6 & (R1L3);


--R1L5 is 74157:inst22|22~44
--operation mode is normal

R1L5 = key7 & (HB21_8) # !key7 & (HB21_8 & KB5L1 # !HB21_8 & (R1L4));


--AB21_16 is cepin:inst9|74175:inst9|16
--operation mode is normal

AB21_16_lut_out = HB5_6;
AB21_16 = DFFEAS(AB21_16_lut_out, !inst13, cl, , , , , , );


--KB1L1 is cepin:inst9|24x4:inst13|74151:inst|f74151:sub|73~14
--operation mode is normal

KB1L1 = !HB21_7 & (HB21_6 # AB21_16);


--R1L6 is 74157:inst22|22~45
--operation mode is normal

R1L6 = key7 & (R1L5 & (KB1L1) # !R1L5 & R1L2) # !key7 & (R1L5);


--EB1L1 is dtxs:inst5|7447:inst|81~7
--operation mode is normal

EB1L1 = R1L21 & (R1L42 # R1L81 & !R1L6) # !R1L21 & (R1L81 & (!R1L6) # !R1L81 & !R1L42 & R1L6);


--EB1L2 is dtxs:inst5|7447:inst|82~42
--operation mode is normal

EB1L2 = R1L21 & (R1L42 # R1L81 & !R1L6) # !R1L21 & (R1L81 & R1L6);


--EB1_83 is dtxs:inst5|7447:inst|83
--operation mode is normal

EB1_83 = R1L81 & R1L42 # !R1L81 & (R1L21 & !R1L6);


--EB1L4 is dtxs:inst5|7447:inst|84~51
--operation mode is normal

EB1L4 = R1L6 & (R1L81 $ !R1L21) # !R1L6 & R1L81 & !R1L21;


--EB1_85 is dtxs:inst5|7447:inst|85
--operation mode is normal

EB1_85 = R1L6 # R1L81 & (!R1L21);


--EB1L6 is dtxs:inst5|7447:inst|86~41
--operation mode is normal

EB1L6 = R1L21 & (R1L6 # !R1L81) # !R1L21 & R1L6 & !R1L42 & !R1L81;


--EB1_87 is dtxs:inst5|7447:inst|87
--operation mode is normal

EB1_87 = R1L21 & R1L6 & R1L81 # !R1L21 & (!R1L81 & !R1L42);


--AB81_15 is 10jcq_zong:inst41|74175:inst2|15
--operation mode is normal

AB81_15_lut_out = AB3_15;
AB81_15 = DFFEAS(AB81_15_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[9] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[9]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[9]_PORT_A_address_reg = DFFE(LB1_q_a[9]_PORT_A_address, LB1_q_a[9]_clock_0, , , );
LB1_q_a[9]_clock_0 = DB01_87;
LB1_q_a[9]_PORT_A_data_out = MEMORY(, , LB1_q_a[9]_PORT_A_address_reg, , , , , , LB1_q_a[9]_clock_0, , , , , );
LB1_q_a[9]_PORT_A_data_out_reg = DFFE(LB1_q_a[9]_PORT_A_data_out, LB1_q_a[9]_clock_0, , , );
LB1_q_a[9] = LB1_q_a[9]_PORT_A_data_out_reg[0];


--Y1_inst11 is 9or:inst42|inst11
--operation mode is normal

Y1_inst11 = AB81_15 # LB1_q_a[9];


--AB81_16 is 10jcq_zong:inst41|74175:inst2|16
--operation mode is normal

AB81_16_lut_out = AB3_16;
AB81_16 = DFFEAS(AB81_16_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[8] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[8]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[8]_PORT_A_address_reg = DFFE(LB1_q_a[8]_PORT_A_address, LB1_q_a[8]_clock_0, , , );
LB1_q_a[8]_clock_0 = DB01_87;
LB1_q_a[8]_PORT_A_data_out = MEMORY(, , LB1_q_a[8]_PORT_A_address_reg, , , , , , LB1_q_a[8]_clock_0, , , , , );
LB1_q_a[8]_PORT_A_data_out_reg = DFFE(LB1_q_a[8]_PORT_A_data_out, LB1_q_a[8]_clock_0, , , );
LB1_q_a[8] = LB1_q_a[8]_PORT_A_data_out_reg[0];


--Y1_inst10 is 9or:inst42|inst10
--operation mode is normal

Y1_inst10 = AB81_16 # LB1_q_a[8];


--AB71_13 is 10jcq_zong:inst41|74175:inst1|13
--operation mode is normal

AB71_13_lut_out = AB2_13;
AB71_13 = DFFEAS(AB71_13_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[7] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[7]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[7]_PORT_A_address_reg = DFFE(LB1_q_a[7]_PORT_A_address, LB1_q_a[7]_clock_0, , , );
LB1_q_a[7]_clock_0 = DB01_87;
LB1_q_a[7]_PORT_A_data_out = MEMORY(, , LB1_q_a[7]_PORT_A_address_reg, , , , , , LB1_q_a[7]_clock_0, , , , , );
LB1_q_a[7]_PORT_A_data_out_reg = DFFE(LB1_q_a[7]_PORT_A_data_out, LB1_q_a[7]_clock_0, , , );
LB1_q_a[7] = LB1_q_a[7]_PORT_A_data_out_reg[0];


--Y1_inst9 is 9or:inst42|inst9
--operation mode is normal

Y1_inst9 = AB71_13 # LB1_q_a[7];


--AB71_14 is 10jcq_zong:inst41|74175:inst1|14
--operation mode is normal

AB71_14_lut_out = AB2_14;
AB71_14 = DFFEAS(AB71_14_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[6] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[6]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[6]_PORT_A_address_reg = DFFE(LB1_q_a[6]_PORT_A_address, LB1_q_a[6]_clock_0, , , );
LB1_q_a[6]_clock_0 = DB01_87;
LB1_q_a[6]_PORT_A_data_out = MEMORY(, , LB1_q_a[6]_PORT_A_address_reg, , , , , , LB1_q_a[6]_clock_0, , , , , );
LB1_q_a[6]_PORT_A_data_out_reg = DFFE(LB1_q_a[6]_PORT_A_data_out, LB1_q_a[6]_clock_0, , , );
LB1_q_a[6] = LB1_q_a[6]_PORT_A_data_out_reg[0];


--Y1_inst8 is 9or:inst42|inst8
--operation mode is normal

Y1_inst8 = AB71_14 # LB1_q_a[6];


--AB71_15 is 10jcq_zong:inst41|74175:inst1|15
--operation mode is normal

AB71_15_lut_out = AB2_15;
AB71_15 = DFFEAS(AB71_15_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[5] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[5]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[5]_PORT_A_address_reg = DFFE(LB1_q_a[5]_PORT_A_address, LB1_q_a[5]_clock_0, , , );
LB1_q_a[5]_clock_0 = DB01_87;
LB1_q_a[5]_PORT_A_data_out = MEMORY(, , LB1_q_a[5]_PORT_A_address_reg, , , , , , LB1_q_a[5]_clock_0, , , , , );
LB1_q_a[5]_PORT_A_data_out_reg = DFFE(LB1_q_a[5]_PORT_A_data_out, LB1_q_a[5]_clock_0, , , );
LB1_q_a[5] = LB1_q_a[5]_PORT_A_data_out_reg[0];


--Y1_inst7 is 9or:inst42|inst7
--operation mode is normal

Y1_inst7 = AB71_15 # LB1_q_a[5];


--AB71_16 is 10jcq_zong:inst41|74175:inst1|16
--operation mode is normal

AB71_16_lut_out = AB2_16;
AB71_16 = DFFEAS(AB71_16_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[4] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[4]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[4]_PORT_A_address_reg = DFFE(LB1_q_a[4]_PORT_A_address, LB1_q_a[4]_clock_0, , , );
LB1_q_a[4]_clock_0 = DB01_87;
LB1_q_a[4]_PORT_A_data_out = MEMORY(, , LB1_q_a[4]_PORT_A_address_reg, , , , , , LB1_q_a[4]_clock_0, , , , , );
LB1_q_a[4]_PORT_A_data_out_reg = DFFE(LB1_q_a[4]_PORT_A_data_out, LB1_q_a[4]_clock_0, , , );
LB1_q_a[4] = LB1_q_a[4]_PORT_A_data_out_reg[0];


--Y1_inst6 is 9or:inst42|inst6
--operation mode is normal

Y1_inst6 = AB71_16 # LB1_q_a[4];


--AB61_13 is 10jcq_zong:inst41|74175:inst|13
--operation mode is normal

AB61_13_lut_out = AB1_13;
AB61_13 = DFFEAS(AB61_13_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[3] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[3]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[3]_PORT_A_address_reg = DFFE(LB1_q_a[3]_PORT_A_address, LB1_q_a[3]_clock_0, , , );
LB1_q_a[3]_clock_0 = DB01_87;
LB1_q_a[3]_PORT_A_data_out = MEMORY(, , LB1_q_a[3]_PORT_A_address_reg, , , , , , LB1_q_a[3]_clock_0, , , , , );
LB1_q_a[3]_PORT_A_data_out_reg = DFFE(LB1_q_a[3]_PORT_A_data_out, LB1_q_a[3]_clock_0, , , );
LB1_q_a[3] = LB1_q_a[3]_PORT_A_data_out_reg[0];


--Y1_inst5 is 9or:inst42|inst5
--operation mode is normal

Y1_inst5 = AB61_13 # LB1_q_a[3];


--AB61_14 is 10jcq_zong:inst41|74175:inst|14
--operation mode is normal

AB61_14_lut_out = AB1_14;
AB61_14 = DFFEAS(AB61_14_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[2] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[2]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[2]_PORT_A_address_reg = DFFE(LB1_q_a[2]_PORT_A_address, LB1_q_a[2]_clock_0, , , );
LB1_q_a[2]_clock_0 = DB01_87;
LB1_q_a[2]_PORT_A_data_out = MEMORY(, , LB1_q_a[2]_PORT_A_address_reg, , , , , , LB1_q_a[2]_clock_0, , , , , );
LB1_q_a[2]_PORT_A_data_out_reg = DFFE(LB1_q_a[2]_PORT_A_data_out, LB1_q_a[2]_clock_0, , , );
LB1_q_a[2] = LB1_q_a[2]_PORT_A_data_out_reg[0];


--Y1_inst4 is 9or:inst42|inst4
--operation mode is normal

Y1_inst4 = AB61_14 # LB1_q_a[2];


--AB61_15 is 10jcq_zong:inst41|74175:inst|15
--operation mode is normal

AB61_15_lut_out = AB1_15;
AB61_15 = DFFEAS(AB61_15_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[1] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[1]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[1]_PORT_A_address_reg = DFFE(LB1_q_a[1]_PORT_A_address, LB1_q_a[1]_clock_0, , , );
LB1_q_a[1]_clock_0 = DB01_87;
LB1_q_a[1]_PORT_A_data_out = MEMORY(, , LB1_q_a[1]_PORT_A_address_reg, , , , , , LB1_q_a[1]_clock_0, , , , , );
LB1_q_a[1]_PORT_A_data_out_reg = DFFE(LB1_q_a[1]_PORT_A_data_out, LB1_q_a[1]_clock_0, , , );
LB1_q_a[1] = LB1_q_a[1]_PORT_A_data_out_reg[0];


--Y1_inst3 is 9or:inst42|inst3
--operation mode is normal

Y1_inst3 = AB61_15 # LB1_q_a[1];


--AB61_16 is 10jcq_zong:inst41|74175:inst|16
--operation mode is normal

AB61_16_lut_out = AB1_16;
AB61_16 = DFFEAS(AB61_16_lut_out, A1L12, cl, , , , , , );


--LB1_q_a[0] is two_rom:inst33|altsyncram:altsyncram_component|altsyncram_bop:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
LB1_q_a[0]_PORT_A_address = BUS(AB31_16, AB31_15, AB31_14, AB31_13, AB41_16, AB41_15, AB41_14, AB41_13, AB51_16, AB51_15, AB51_14, AB51_13);
LB1_q_a[0]_PORT_A_address_reg = DFFE(LB1_q_a[0]_PORT_A_address, LB1_q_a[0]_clock_0, , , );
LB1_q_a[0]_clock_0 = DB01_87;
LB1_q_a[0]_PORT_A_data_out = MEMORY(, , LB1_q_a[0]_PORT_A_address_reg, , , , , , LB1_q_a[0]_clock_0, , , , , );
LB1_q_a[0]_PORT_A_data_out_reg = DFFE(LB1_q_a[0]_PORT_A_data_out, LB1_q_a[0]_clock_0, , , );
LB1_q_a[0] = LB1_q_a[0]_PORT_A_data_out_reg[0];


--Y1_inst is 9or:inst42|inst
--operation mode is normal

Y1_inst = AB61_16 # LB1_q_a[0];


--GB1_q_a[9] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[9]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[9]_PORT_A_address_reg = DFFE(GB1_q_a[9]_PORT_A_address, GB1_q_a[9]_clock_0, , , );
GB1_q_a[9]_clock_0 = DB01_87;
GB1_q_a[9]_PORT_A_data_out = MEMORY(, , GB1_q_a[9]_PORT_A_address_reg, , , , , , GB1_q_a[9]_clock_0, , , , , );
GB1_q_a[9]_PORT_A_data_out_reg = DFFE(GB1_q_a[9]_PORT_A_data_out, GB1_q_a[9]_clock_0, , , );
GB1_q_a[9] = GB1_q_a[9]_PORT_A_data_out_reg[0];


--GB1_q_a[8] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[8]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[8]_PORT_A_address_reg = DFFE(GB1_q_a[8]_PORT_A_address, GB1_q_a[8]_clock_0, , , );
GB1_q_a[8]_clock_0 = DB01_87;
GB1_q_a[8]_PORT_A_data_out = MEMORY(, , GB1_q_a[8]_PORT_A_address_reg, , , , , , GB1_q_a[8]_clock_0, , , , , );
GB1_q_a[8]_PORT_A_data_out_reg = DFFE(GB1_q_a[8]_PORT_A_data_out, GB1_q_a[8]_clock_0, , , );
GB1_q_a[8] = GB1_q_a[8]_PORT_A_data_out_reg[0];


--GB1_q_a[7] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[7]_PORT_A_address = BUS(AB1_16, AB1_15, AB1_14, AB1_13, Z5L4, Z5L5, Z5_44, Z5_45, Z6_42, Z6_43, Z6_44, Z6_45);
GB1_q_a[7]_PORT_A_address_reg = DFFE(GB1_q_a[7]_PORT_A_address, GB1_q_a[7]_clock_0, , , );
GB1_q_a[7]_clock_0 = DB01_87;
GB1_q_a[7]_PORT_A_data_out = MEMORY(, , GB1_q_a[7]_PORT_A_address_reg, , , , , , GB1_q_a[7]_clock_0, , , , , );
GB1_q_a[7]_PORT_A_data_out_reg = DFFE(GB1_q_a[7]_PORT_A_data_out, GB1_q_a[7]_clock_0, , , );
GB1_q_a[7] = GB1_q_a[7]_PORT_A_data_out_reg[0];


--GB1_q_a[6] is Sine_rom:inst7|altsyncram:altsyncram_component|altsyncram_0sp:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1